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Planar fully-depleted SOI technology with ultra-thin body and buried oxide presents a platform for an energy-efficient design in deeply scaled technologies without major changes in the bulk-CMOS design infrastructure. Good control of short-channel effects with thin transistor body offers a possibility to reduce the supply voltage. Thin buried oxide provides threshold tuning via body bias. Overall...
With the technology scaling down to the deep sub-micron domain, leakage power increases rapidly in VLSI, enhancing the area overhead of dynamic power management system. Reverse Body Bias(RBB) is a common method to reduce the leakage power at run-time. To overcome the larger area overhead of controller applied on RBB, this paper proposes a new way of connection, which can reduce area of controller...
The optimization of the noise performance of integrated complementary metal-oxide semiconductor (CMOS) charge amplifiers is studied in detail considering accurate 1/f noise modeling for the input metal-oxide semiconductor field-effect transistor (MOSFET) biased in a strong inversion-saturation region. This paper aims to generalize and correct previously published analyses which have been based on...
Reducing power consumption is one of the important design goals for circuit designers. Power optimization techniques for bulk CMOS-based circuit designs have been extensively studied. As technology scales, FinFET has been proposed as an alternative for bulk CMOS when technology scales beyond 32 nm technology (E.J. Nowak et al., 2004). In this paper, we propose a power optimization framework for FinFET...
The multi-threshold-voltage CMOS (MTCMOS) technique is very effective for reducing leakage power. Previously, sleep transistors were connected the virtual ground lines to reduce the power consumption, and a distributed sleep transistor network (DSTN) was proposed to reduce the instantaneous current. This paper presents a research on how to find the near optimal solution for the sleep transistor sizing...
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