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Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
The rate compatible punctured convolutional code (RCPC code) is an important module in Multi-band Orthogonal Frequency Division Multiplexing Ultra Wide Band (MB-OFDM-UWB) indoor positioning system introduced in this paper as a kind of useful channel coding to offer more protection against all kinds of channel noise under indoor channel environments. In this paper, RCPC code for MB-OFDM-UWB indoor...
Li and Xia have recently investigated the design of space-time codes that achieve full spatial diversity for asynchronous cooperative communications. They show that certain of the binary space-time trellis codes derived from the Hammons-El Gamal stacking construction are delay tolerant and can be used in the multilevel code constructions by Lu and Kumar to produce delay tolerant space-time codes for...
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