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This paper focuses on the design and verification methods of distributed logic controllers supervising real-life processes. Such systems have to be designed very carefully and precisely in order to operate flawlessly and to meet user needs. We propose to use interpreted Petri nets as modeling formalism. A new design flow of distributed logic controllers is introduced. The methodology covers the development...
In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader,...
In HW/SW co-simulation based logic verification systems, the design under test (DUT) is executed on an FPGA based emulator and the behavioral testbench written in some high level language like C or HDL is run on a SW simulator or a general purpose CPU. In such systems it is essential to reduce the communication between SW and HW sides to enhance overall verification speed. Therefore it is of significant...
Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification of industrial embedded systems, forcing the designer to implement ad-hoc verification solutions. This contribution presents a suitable solution for long-term verification of FPGA-based designs consisting on a verification core that uses the Picoblaze microcontroller, dedicated logic...
Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(System-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented...
We propose a high level synthesis approach to generate RT level hardware from a specification of operation properties. The property language is called InTerval language (ITL) and we assume the set of properties is complete, such that the properties alone are strong enough to map every possible sequence of input data to exactly one sequence of output data. A major advantage of using operation properties...
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