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Due to the larger scale of power systems and larger number of converters involved, the simulation of power systems becomes slower, with lower accuracy. FPGA is the new generation computation hardware, which is an integrated circuit designed for a special function. However, FPGA simulation still requires the parallel technology to extend the simulation scale. Network tearing interfaces can be used...
FPGA capacity is quickly outpacing designer's productivity and limiting the ability to exploit FPGA processing resources. Model-based synthesis, where a high level behavioral model is used for fast design iteration, which is then synthesizable directly into FPGA object code has been proposed as a solution. Several orders of magnitude difference in simulation speed have been observed between different...
Power electronic systems do not always operate under ideal condition because of the conflict between computational efficiency and simulation precision. In addition, there is significant computation burden in real-time simulation of voltage source converter closed-loop control. Hence, the power electronic real-time co-simulation design based on FPGA+DSP+PC architecture is put forward. The design adopts...
In order to carry out high speed and effective digital image processing, the use of FPGA is a relatively reasonable choice due to the large amount of data in digital image. Thus we need a careful simulation test to verify the correctness of the VHDL code to achieve the corresponding algorithm. It is difficult to achieve the digital image processing algorithm simulation if we rely on the traditional...
As for nervous diseases study, building specific models tends to be really hard but significant. This paper introduces a novel method for neuron system identification using nonlinear auto-regressive Volterra (NARV) model based on the field programmable gate arrays (FPGA). We select HH model as a “black-box” system requiring identification, and obtain input and output data. A NARV model built on the...
This paper presents a configurable and observable model of L1 data cache memory and a novel method for integrating the model into an FPGA prototype. Embedded system software designers use in-circuit emulation on FPGA platforms to validate the functionality and performance of embedded software. Data cache, particularly L1, has a major impact of system performance, yet remains unobservable during software...
This paper deals with the mathematical modelling of a scheduling problem in a heterogeneous CPU/FPGA architecture with communication delay in order to minimize the makespan, Cmex. This study was motivated by the quality of the available solvers for Mixed Integer Program. The proposed model includes the communication delay constraints in a general form in a heterogeneous case depending at the same...
Real-time computing systems are increasingly used in several industrial domains such as aerospace, avionic, rail, and automotive. During the manufacturing process, designers need development tools for the verification and the validation (V&V) of modern and complex systems. Today, the simulation phase is considered as an unavoidable part of the V&V cycle. In order to meet the application requirements...
In this paper, an improved sun-tracking system using the FPGA chip as controlling platform is proposed. The system computes the sun trails precisely through tracking algorithm, chooses different tracking frequencies in accordance with illumination intensity, and the tracking precision is guaranteed by the angle-sensor which can detect mechanical deviation. The simulating test shows that this system...
Digital controllers based on specific hardware (FPGA or ASIC) described in hardware description languages (HDL), such as VHDL or Verilog, have been applied to low or medium DC/DC switching power converters in the last years. Standard designs procedures of DC/DC power converters involves the simulation of the whole converter, including analog power stage and digital control stage. Co-simulation of...
Estimating parametric curves from images using robust fitting algorithms is a well-known and important computer vision task. We present a complete FPGA design and implementation of a fast and robust model fitting algorithm for real-time ellipse detection on video streams. The proposed solution relies on a the RANSAC algorithm, modified for FPGA deployment, in combination with an image-preprocessing...
Modern embedded systems are characterized by a heterogeneous architecture including several modules (e.g., DSPs, memories and mixed-signal IPs) often integrated with one or more microprocessor cores controlling the system functionalities by means of embedded software programs. The verification of such a kind of systems has become a challenge due to their increasing complexity that makes traditional...
As processor performance continues to outgrow memory capacity and bandwidth, system and application performance has become constrained by the memory subsystem. Promising new technologies like Phase Change Memory (PCM) and Flash have emerged which may add capacity at a cost cheaper than conventional DRAM, but at the cost of added latency and poor endurance. It is likely that systems leveraging these...
We describe the design and implementation of an FPGA-based architecture for real-time simulation of spiking neural networks that include gap junctions, a type of synapse not often used in neural models due to their high computational cost. Recent research suggests that electrical synapses or gap junctions play a role in synchronizing the activity of larger groups of neurons in the brain, and are potentially...
Reducing time to market, design cost and fast developing, prototyping and testing of embedded industrial and automation models are very interesting topics in recent manufacturing and industry methodologies. In recent years, Model driven architecture or engineering methodology has been introduced in the field of software engineering by OMG. This methodology separate platform independent, and platform...
The RLS identification algorithm has been widely used in many fields. FPGA implements RLS algorithm parallel and pipeline. In this paper, we build the RLS algorithm model using DSP Builder based on the circuit model of fuel cell stack, and then use collected voltage and current data to simulate. Results prove the correctness of the design, and that it is simpler and faster by using DSP Builder to...
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). To reduce the power dissipation we use the CIC filter to perform an efficient decimation, and then follow it with a finite impulse response (FIR) compensation filter that runs at a reduced sampling rate. The final results and performance measures are quantified...
In Digital Signal Processing, trigonometry and complex multiplications are used in many signal equations, such as synchronization and equalization. Therefore, a fast and an efficient method to calculate trigonometry and complex multiplications are required. Coordinate Rotation Digital Computer (CORDIC) is trigonometric algorithm that is used to transforming data from rectangular to polar and vice...
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). The designed DDC is one of the modules in the receiver of the base station in a wireless local positioning systems (WLPS). WLPS is capable of localization in the GPS-denied environments such as indoor and underground. The final results and performance measures...
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). The designed DDC is one of the modules in the receiver of the base station in a wireless local positioning systems (WLPS). WLPS is capable of localization in the GPS-denied environments such as indoor and underground. The final results and performance measures...
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