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A receiver structure based on a joint LDPC decoding and synchronization algorithm and realized on an FPGA platform is introduced. The realization system achieves the BER of 1e-5 at the channel SNR of -4.6 dB with moderate hardware complexity, and the performance degradation is less than 1.3 dB from the ideal situation. So it is suitable for deep space communications and other wireless communications.
In this paper the implementation of a configurable hardware for an UHF RF identification (RFID) tag emulator at 868 MHz is demonstrated. The tag emulator is used for reader performance verification under worst case conditions. The characteristics of a tag can precisely be emulated: reflection coefficient dependent on received signal strength, variation of the frequency, and timing jitter of the backscattered...
We present an algorithm and real time implementation for rapid code phase synchronization to direct sequence spread spectrum signals. The synchronization algorithm utilizes a complex matched filter to achieve code synchronization without sequential search over code phases, significantly reducing synchronization time. The algorithm is implemented on a Xilinx Spartan FPGA and is highly tailored to exploit...
This paper presents our design for a real-time image transmission system based on OFDM and our practical implementation of it. We described many blocks required for the OFDM system, while paying particular attention to the synchronization algorithm. Simulation results demonstrate that the proposed transmission technique is robust for mobile subscriber and can be employed efficiently in an OFDM system...
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