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In earlier work, we suggested a low cost control communication scheme across half-duplex Ethernet allowing for reduced jitter and delay for an information sharing control communication bus. The principle advantage of half-duplex Ethernet is the reduced number of wires (two versus four wires) and the reduced cost of switch/router equipment. The basic principles for our communication has been the network...
An approach for cheap and deterministic control communication using Ethernet real-time control communication is presented. Field-programmable gate array (FPGA) technology, i.e Xilinx XC3S500E from the Spartan-3E family, is used to implement the Ethernet communication strategy. The unit is defined in Verilog using Xilinx ISE 11.1 software tools. Data packages are sent at well defined times to avoid...
By proposing the framework of global robust ℋ-/ℋ∞ synchronization, this study focuses on the robust fault detection issue within the synchronization for a class of nonlinear dynamical networks composed by identical Lur'e systems. Under such synchronization scheme, the error dynamical system is globally asymptotically stable, the effect of external disturbances is suppressed, and at the same time,...
Spatiotemporal activity of a hippocampal CA3 model and its dynamic features were investigated. The CA3 model consists of 256 pyramidal cells and 25 inhibitory interneurons. Each pyramidal cell is a single-compartment model which was reduced from the 19-compartment cable model of the CA3 pyramidal cell developed by . Each interneuron is a model which causes tonic responses to constant depolarizing...
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