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In this paper, we designed a 9T SRAM cell using dual voltage threshold (DVT) and stacking effect. To achieve high density, low power and high performance, device scaling has been continuously done that result in increase in leakage power dissipation. At sub-micron technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper is to analyze the Performance...
Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay,...
A group of new memory circuit techniques with the emerging FinFET technology are evaluated in this paper. Three independent-gate FinFET SRAM cells and two multi-threshold-voltage (multi-Vt) work-function engineered SRAM cells are compared for data stability, leakage power consumption, and cell area. The highest read stability is provided by the technique based on dynamically tuning the threshold voltages...
A new seven transistors (7T) dual threshold voltage SRAM cell is proposed in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the read speed. With the new 7T SRAM cell, the storage nodes are isolated from the bitlines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T)...
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