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Static Random Access Memory (SRAM) is the most popular circuit which is used in all processors and occupies the considerable area of the chip. The total power consumption of circuit is largely dependent on power dissipated by memory. There were several efforts for reduction in power consumption such as Power Gated SRAM circuits and increasing virtual ground voltage. The previous techniques were capable...
A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42...
Data stability is a primary concern in today's high performance memory circuits with deeply scaled transistors and power supply voltages. Recently proposed eight-transistor (8T) Static Random Access Memory (SRAM) cells offer enhanced data stability as compared to the conventional six-transistor (6T) SRAM cells by isolating the bitlines from data storage nodes during a read operation. Novel multi-threshold-voltage...
Conventional six-transistor (6T) memory cell has an intrinsic data stability problem due to directly-accessed storage nodes during a read operation. The data stability issue becomes more severe with increasing variability and decreasing supply voltage in scaled CMOS technologies. Conventional techniques to enhance the data stability of 6T memory cells tend to sacrifice other important figures of merit,...
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by...
Ground bouncing noise produced during the sleep to active mode transitions is an important reliability concern in multi-domain Multi-Threshold CMOS (MTCMOS) integrated circuits. Ground bouncing noise, leakage power consumption, and data stability of MTCMOS flip-flops are evaluated in this paper. The effectiveness of different circuit techniques is discussed for achieving lower noise during the reactivation...
Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay,...
Reactivation noise is an important reliability concern in standard sequential MTCMOS circuits. The ground bouncing noise, the leakage power consumption, and the data stability of various sequential MTCMOS circuits are evaluated in this paper. The attractive application space of different data retention MTCMOS circuit techniques is identified for various design metrics with a 90 nm CMOS technology.
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