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Static Random Access Memory (SRAM) is the most popular circuit which is used in all processors and occupies the considerable area of the chip. The total power consumption of circuit is largely dependent on power dissipated by memory. There were several efforts for reduction in power consumption such as Power Gated SRAM circuits and increasing virtual ground voltage. The previous techniques were capable...
A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42...
A new asymmetrical ground gated 7T SRAM circuit technique is presented in this paper to lower leakage currents and enhance noise immunity in idle memory banks. A novel write assist scheme is proposed to enhance write margin with the new memory circuit. The leakage power consumption is suppressed by up to 4.30× and the data stability is enhanced by up to 4.79× as compared with the previously published...
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by...
Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay,...
A group of new memory circuit techniques with the emerging FinFET technology are evaluated in this paper. Three independent-gate FinFET SRAM cells and two multi-threshold-voltage (multi-Vt) work-function engineered SRAM cells are compared for data stability, leakage power consumption, and cell area. The highest read stability is provided by the technique based on dynamically tuning the threshold voltages...
Data stability of Static Random Access Memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A six transistor (6T) SRAM cell based on independent-gate FinFET technology (IG-FinFET) is described in this...
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