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A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by...
Ground bouncing noise produced during the sleep to active mode transitions is an important reliability concern in multi-domain Multi-Threshold CMOS (MTCMOS) integrated circuits. Ground bouncing noise, leakage power consumption, and data stability of MTCMOS flip-flops are evaluated in this paper. The effectiveness of different circuit techniques is discussed for achieving lower noise during the reactivation...
Reactivation noise is an important reliability concern in standard sequential MTCMOS circuits. The ground bouncing noise, the leakage power consumption, and the data stability of various sequential MTCMOS circuits are evaluated in this paper. The attractive application space of different data retention MTCMOS circuit techniques is identified for various design metrics with a 90 nm CMOS technology.
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