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In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage...
In this work, we present a novel 8T SRAM cell that enhances the stability of built-in data storage elements. During a read operation, the proposed cell suppresses a noise-vulnerable ‘0’ node rising, and hence exhibiting near-ideal butterfly curve essential for robust SRAM bit-cell design. The cell itself bears an improved variability tolerance which gives much tight stability distribution across skewed...
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