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This paper presents transistor variability modeling and its validation for body-biased subthreshold circuits based on measurements of a device-array circuit using a 90-nm technology. The device array consists of p/nMOS transistors and ring oscillators. We examine and confirm the correlation between the performance variation model extracted from measured I-V characteristics and fabricated oscillation...
Measured variabilities from 0.35 mum to 90 nm processes are explained with a growing concern of within-die components. Variability impact on circuit performance is discussed. A possible approach for mitigating the variability is the introduction of layout regularity, and its effect is examined by test structures in a 90 nm process and lithography simulation in a 45 nm process.
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