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Most of the links in future wireless communication networks will be established over relatively short distances. This new direction in wireless communication is adopted and being developed by embedded multimedia applications leaders. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around...
The European ARTEMIS ACROSS project aims to overcome the limitations of existing Multi-Processor System-on-a-Chip (MPSoC) architectures with respect to safety-critical applications. MPSoCs have a tremendous potential in the domain of embedded systems considering their enormous computational capacity and energy efficiency. However, the currently existing MPSoC architectures have significant limitations...
When migrating to future technology nodes, dependability becomes a major design problem as variability, aging and susceptibility to soft errors increase. The purpose of this program is to research cross-layer solutions that address the physical problems at system-level i.e. at hardware-level, operating system level, application level etc. The goals and an overview of the DFG SPP 1500 research program...
In this paper, we describe design and implementation of the Dependable Responsive Multithreaded Processor (D-RMTP) SoC (System-on-a-Chip) and SiP (System-in-a-Package). The D-RMTP SoC provides almost all functions required for the humanoid robots, including a real-time processing unit, a real-time inter-node communication link with error correction, and various I/O peripherals. The D-RMTP SoC is implemented...
Nowadays highly dependable electronic devices are demanded by many safety-critical applications. Dependability attributes such as reliability and availability/maintainability of a many-processor system-on-chip (MPSoC) should already be examined at the design phase. Design for dependability approaches such as using available fault-free processor-cores and introducing a dependability manager infrastructural...
A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and...
Nowadays, safety-critical systems in for instance the automotive industry routinely consist of complex Systems-on-Chip in increasingly advanced processes. The decreased reliability for advanced processes, along with the harsh environmental conditions in cars, causes serious concerns for the dependability of those SoCs. For this reason, some digital IP vendors for those systems are already starting...
An 80 Gbps dependable communication SoC with four 4X PCIe Rev.2.0 ports has been developed that acts as a communication link with high transfer capability. By using the PCIe I/F, the SoC can address two computing nodes as peers, breaking the traditional PCIe limit of only linking to a single master processor. The SoC also employs an intelligent ICU that supports an initiate data transfer function...
Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC...
Heterogeneous SoC devices, including sensors, analogue and mixed-signal front-end circuits and the availability of massive digital processing capability, are being increasingly used in safety-critical applications like in the automotive, medical, and the security arena. Already a significant amount of attention has been paid in literature with respect to the dependability of the digital parts in heterogeneous...
Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential...
As CMOS process technology advances towards 32 nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural...
Physical and environmental variations require the addition of safety margins to the clock frequency of digital systems, making it overly conservative. Aggressive, but reliable, dynamic clock frequency tuning mechanisms that achieve higher system performance, by adapting the clock rates beyond worst case limits, have been proposed earlier. Even though reliable over-clocking guarantees functional correctness,...
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satisfactorily with increasing transistor counts. In conjunction with the increasing rates of transient faults in logic and memory associated with the continuous reduction of feature sizes, this situation creates the need for...
This paper presents a methodology for designing system-on-chip (SOC) interconnection architectures providing a high level of protection from crosstalk effects. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and, thus, designers can easily...
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