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This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been...
The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Low latency SAR ADC has been implemented by detecting two bits per clock cycle. Major contribution of this paper is that it uses only two capacitive DACs instead of three capacitive DACs. This is achieved by using...
In this paper, the high frequency mathematical model based on controlled objects of tri-phase tri-wire diode-clamped tri-level rectifier in tri-dimensional alphabetagamma coordinates has been presented. This mathematical model shows that switch function Sgamma has only effect on the voltage difference of up and down capacitor in DC side and has no effect on line current in AC side and DC output voltage...
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