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Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to...
Massive parallel computing performed on many-core Network-on-Chips (NoCs) is the future of the computing. One feasible approach to implement parallel computing is to deploy multiple applications on the NoC simultaneously. In this paper, we propose a multi-application mapping method starting with the application mapping which finds a region on the NoC for each application and then task mapping which...
This work studies the general method of modern graphics processing unit (GPU) calculating and uses compute unified device architecture (CUDA) to present an implementation of facial expression recognition. We calculate the Gromov-Hausdorff distance between faces, and this measures how far each pair of faces are from being isometric. Finally, The results showed the feasibility of this type of device...
Dynamic spectrum access (DSA) supporting opportunistic transmission without extra spectrum bandwidth is attractive for future wireless communication. To facilitate such DSA system, a power-efficient (green) communication processor is needed to support extremely high speed operation on a power-limited mobile device. Traditional general-purpose and digital signal processors are unable to simultaneously...
Scheduling parallel applications on heterogeneous processors/architectures with different computational speed is a difficult problem. Here, a tabu search metaheuristic is developed to improve the schedule generated by list scheduling. Three neighbourhoods variants are proposed and examined, including a novel neighbourhood that takes the shape of the task graph into account. The effectiveness is evaluated...
In domains of VLSI and the rising SoC, the system design exceedingly depends on the simulation and modeling. Conventional HDLs have some weakness including the extravagant precision and the slow speed. On the other hand, the system-level modeling, such as SystemC, has been widely used on all kinds of projects and achieved favorable results. When the target system scales excessively up, the simulation...
High performance computing (HPC) by parallel computing effort faces several challenges. The first challenge is the efficient design and management of the parallel computing resources of the hardware platform. The second challenge is the transformation of the sequential program meant for classic Von Neumann architecture to explicit parallel instruction computing (EPIC) architecture. The third challenge...
Graphics processing units (GPUs) have been widely used to accelerate algorithms that exhibit massive data parallelism or task parallelism. When such parallelism is not inherent in an algorithm, computational scientists resort to simply replicating the algorithm on every multiprocessor of a NVIDIA GPU, for example, to create such parallelism, resulting in embarrassingly parallel ensemble runs that...
Multi-core processor architectures are gaining huge interests from academia and industry. The multi-core architectures have been proposed and designed for overcoming diminishing return and for efficiently utilizing the exponentially increasing number of transistors available in nano-meter semiconductor technology. Though the multi-core architecture has been proposed as a promising alternative to a...
The following topics are dealt with: advanced robotics; distributed computing; parallel computing; education; health care; national security; mobile computing; multimedia; data security; network security; signal processing; telecommunication application; Internet
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