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In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective...
In this work, the gate-to-bulk capacitance property of MOS transistors is employed to design high-speed two-stage operational amplifiers (opamp). Traditional design of two-stage opamps recommends MIM or PIP capacitors to avoid instability in closed-loop applications. In addition to area efficiency achieved by replacing these capacitors with MOS transistors, the integration of the opamp would become...
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