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A mobile ad hoc network (MANET) consists of a group of communicating hosts that form an arbitrary network topology by means of any of several wireless communication media. MANET communications represent a diversification in communication technology necessary to solve the stringent end-to-end requirements of QoS-based communication networks. Of the many challenges in this complex distributed system,...
Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which...
This paper introduces a bound-based approach to extract a pre-specified number of statistically-critical paths under process variations. These are the paths with the highest “violation probability,” which indicates the probability that a path would violate a given timing constraint. Our approach requires pre-computation of the violation probability of all the nodes and edges in the circuit timing...
In this paper we investigate the search path when building a wireless mesh network under extended ad-hoc network, and we propose a search method that can reduce power consumption. The route search part and the node part - which can be a mobile PC or a mobile phone, etc. -are combined in the proposed method. Moreover, we aim at improving the efficiency of the communication between nodes under the extended...
This work investigates device performances of an AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high electron mobility transistor (MOS-pHEMT) by using ozone water oxidation treatment. Experiment results indicate that the studied MOS-pHEMT has demonstrated superior device characteristics as compared to a conventional pHEMT without oxidation treatment on the same epitaxial structure. The studied...
A DC-invariant gain control technique is introduced for differential CMOS variable-gain low-noise amplifiers (VG-LNA). Such technique provides an advantage of invariant DC bias current when the RF power gain is tuned over the gain control range. Therefore, the transconductance of NMOS transistor is unchanged, which minimizes the input match detuning. Consequently, the optimal design for noise, gain...
This paper presents a non-conventional CMOS device, which is composed of an nMOSFET and a tunneling field effect transistor (TFET) for driver and load. Based on the measurement data of TFET device published, we have for the first time drawn the Q line of the new designed CMOS compared with the conventional CMOS to verify its feasibility. The static power consumption of it can be optimized and reduced...
In this paper, for the first time, we demonstrate the radio frequency (RF) performance of a junctionless vertical MOSFET (JLVMOS). According to the numerical simulation results, the JLVMOS can obtain higher gm, lower gd, in comparison to a junctionless planar SOI MOSFET. This because the vertical double-gate (DG) scheme truly helps to increase the gate controllability over the channel region, resulting...
To date, optically reconfigurable gate arrays (ORGAs) have been developed to address high-speed operations. During that development, a MEMS dynamic optically reconfigurable gate array architecture was proposed: it perfectly removes the static configuration memory to store a context and uses junction capacitances of photodiodes as dynamic configuration memory to realize high-gate count ORGA-VLSI. However,...
We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional...
In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR ≡ fin height (Hfin)/fin width (Wfin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation...
In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (gm), high cut-off frequency (fτ), and high transconductance generation factor (gm/Id) arc achieved. The numerical results also...
This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has...
A new STI-type FinFET structure with its body region been connected is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. From the simulation results, the STI-type FinFET shows that the short-channel effects (SCEs) and the off-state leakage current are proved to be reduced because the threshold voltage (VTH) roll-off and the drain-induced barrier lowering (DIBL)...
In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~72%) and the retention...
The novel design with the adaptability prevents from unexpected stimulus current for medical safety, since the safety is the prime concern for human use. The prototype of the stimulus driver circuit for micro-stimulator used in implantable device is presented in this paper. For epilepsy control, the target of the driver is to output 30-μA stimulus currents, as the tissue impedance varies within 20~200...
SiGe deposition as a channel layer to promote the channel mobility is a promising way in the development of nano-level MOSFET (metal-oxide-semiconductor field-effect transistor). However, the thermal or mechanical stress between strained SiGe layer and crystalline wafer surface is increased more and easy to generate the dislocation defects, inversely reducing the channel mobility performance. Using...
In this study, we propose a novel bulkSi-based device called dual-channel body-tied (DCBT) MOSFET using the self-aligned process without any extra masks. It reveals that our proposed DCBT FET has excellent S.S., decreased Isd,leak, lower Rsd, reduced Jg,limit, smaller lattice temperature, and higher thermal stability when compared with its DC counterpart. And, for the first time, we will investigate...
A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves...
An analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology is presented in this paper. Occupying 0.23mm2 of silicon area, the baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an Output Buffer (OBUF). The gain of the chain can be controlled by tuning the control voltages of the VGA and...
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