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Recently, high density integrated circuits are packaged in the electronic devices such as smartphones and smartwatches. Power amplifier modules integrated in such devices interact with other circuits due to its inductive components, and may cause the electromagnetic interference issues. To reduce the electromagnetic issues, sputtering technology can be used. In this paper, we present the shielding...
Insulated gate bipolar transistor (IGBT) operates at high current, high power and repeated shock current conditions. Joule heating induced during high current conditions, subsequently raising the temperature of the IGBT module. In this paper, we carried out the DC power cycling test with the 200 A current condition. The temperature distribution and the temperature change process of the whole IGBT...
Low temperature soldering can reduce the thermal damage which is caused by thermal expansion mismatch among various materials in an electronic package. Eutectic Sn58Bi solder is a promising low temperature lead-free solder due to its lower melting temperature. The effects of Ag and Cu additions on melting characteristics, wettability and microstructures of Sn58Bi lead-free solder were investigated...
Sn-3.0Ag-0.5Cu lead-free solder, PCB copper clad laminate and copper thin film substrate were used as experimental materials and the Cu/SAC305/Cu interconnection plate-level structure micro-solder joint was prepared by pulsed hot-pressing welding test. The author aimed at investigating the pulse welding time, pulse welding temperature and welding pressure which influence on the microstructure of solder...
For a limited solder volume interconnect structure, bump interconnect reliability is more sensitive to the growth behavior of the interfacial intermetallic compounds(IMCs). The study of the effect of solder cap thickness on the interfacial diffusion reaction is of great importance to the application of copper pillar bump. Here, we investigated the effect of different solder cap thicknesses on IMCs...
Increasing demands for bandwidth in high performance computing, Fifth-generation (5G) communication, and Internet of Things (IOT) applications have driven the migration to 2.5D and 3D interposers, requiring less high frequency loss and higher ratio of hole depth/dimension for vertical interconnections. Through silicon via (TSV) has been utilized to minimize the distance between chips by vertically...
The reliability of interconnections in microelectronic packages is an urge concern for the well-functioned electronic devices. Owing to the mismatch of CTE of different materials involved in the interconnections, the structures endures high risk of fatigue failure under thermal cycle loading. Numerous fatigue life prediction models have been proposed or developed for the evaluation of reliability...
Via last TSV (through silicon via) technology is more and more applied in 3D WLCSP, which can decrease package volume and increase I/O density. The process of via last includes temporary bonding, grinding, photolithograph, silicon etching, SiO2 etching, CVD, PVD, plating and so on. Silicon etching and SiO2 etching are important process of via last TSV package for interconnect technology. Temporary...
Silicon anodes, with an extreme high theoretical specific capacity of 4200mAh g−1 and proper stable plateau potential of 0.4V, are considered one of the most promising anode materials in rechargeable Lithium-ion batteries. However, the great structural and volumetric changes during charge/discharge cycles relating to poor cycling performance are still the most critical challenges limiting the breakthrough...
With the strength of fine pitch, high electrical conductivity and excellent reliability, copper pillar interconnect becomes a promising alternative to traditional solder bump. However, bad surface smoothness is a severe problem and significantly affects the reliability of the bump connection. In this paper, numerical simulations on the shape evolution of copper pillar bump and the effect of bump dimension...
In order to study the electromigration characteristics of the butting solder joint in microelectronic packaging devices, this paper designs a Cu/Solder/Cu electromigration experiment to observe the change of the microstructure of the interface by scanning electron microscopy (SEM). It is found that the evolvement of the IMC at anode follows a parabolic growth rule under the condition of electric current...
As the electronic packaging density continues to increase, flip chip or stacked packaging via bump bonding is gradually replacing traditional wire bonding and will become the mainstream packaging form in the future. For copper bumps, this new type of electronic interconnection has not yet been fixed by industry standards. Therefore, this paper has made a preliminary study on the reliability of this...
High bandwidth Package on Package (HBPoP) had be well used which replaced FCMAPPOP in high-end mobile products with its advantages of wide I/O counts, high performance and the better integration between application processor and stacked memory packages. The structure of HBPoP is utilized flip-chip technology with ball grid array (BGA) balls on the bottom package and connect top DRAM package with substrate...
Transrating is a bitrate transcoding technique that facilitates video applications in heterogeneous environments. This paper presents a fast coding-unit (CU) mode decision algorithm for transrating a once-encoded HEVC bitstreams to lower bitrate versions of diverse quality levels. The proposed method comprises three major parts. First, an early SKIP decision is based on the modes and motion vectors...
This paper investigates the effect of AC losses on the steady-state temperature rise distribution in concentrated windings of permanent magnet machines with parallel strands by combined electromagnetic and thermal finite-element analyses. The copper losses are decomposed into DC loss, strand-level AC loss and bundle-level AC loss. It shows that the AC losses can significantly increase the winding...
Tin-plated copper structure was widely applied in the electronic products. With the development of the electronics industry, the integration degree increased and the component size reduced obviously. The conventional tin plating technology met the micro-structure challenge; it may not be used in advanced electronic packaging process. The electroless tin plating technology could solve this problem...
The parasitic parameters in the power module have a negative effect on switching losses and dynamic characteristics. With the rapid development of integrated circuit technology, the high current, high frequency and high pressure working environment put forward higher requirements for the switching circuit delay, reliability and power consumption. The rational layout of the power module is the key...
With the development of high density electronic packaging and surface mount assembly, fine pitch package or micro BGA are facing challenges such as miniaturization, high density and assembly problems due to the fine pitch and fine area array assembly limitation. Most fine pitch packages' pitch limited in around 0.3mm pitch. If pitches are smaller than this limitation, the manufacture of packages'...
The particle-free silver and copper conductive ink were used as the reactive inks, respectively. For the Ag ink, during the printing process, a layer of ink drops would be printed. After that, the printed liquid drops were sintered in an oven to obtain a compact silver layer. Repeat the “printing and sintering” process to form a silver film by a layer-by-layer way. The film is consisted of irregular...
For deep ultraviolet light emitting diodes (DUV-LEDs) packaging, the choice of substrate directly affected its performance and reliability. In this paper, a structure was proposed to promote thermal management and lifespan of DUV-LEDs by introducing the ceramic substrate with copper filled thermal hole. The AlN ceramic substrates with different number of copper filled thermal holes were fabricated...
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