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Digital speckle correlation method (DSCM) is used to measure the thermomechanical coupling effect in COB packaging structures. CCD camera is applied to capture the speckle patterns of CMOS chip at different temperature fields. Analyzing the speckle patterns, the in-plane deformation of the CMOS chip is obtained. Based on the trigonometrical theory, out-plane displacement can be obtained by measuring...
In this paper, we demonstrate that by introducing a high tensile Inter Layer Dielectric (ILD) in the fabrication process, the hook shaped saturation drain current (Idsat) behavior of NMOS can be reduced and totally eliminated in PMOS for 0.13um technology node. The hook shaped Idsat behavior is caused by the combination of mechanical stress due to Shallow Trench Isolation (STI) in channel width direction...
3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for...
We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (LG=20nm; W=30nm; TSiGe=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance...
A product-level aging monitor replicating a 40nm CMOS ARM1176 critical path is presented. The monitor enables a separation of the dominating negative bias instability (NBTI) stress, including speed recovery, and the switching-activity dependent hot carrier stress (HCS). The comprehensive analysis comprises transistor and circuit level measurements as well as simulations. The monitor results demonstrate...
Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without...
The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be...
A new electrostatic discharge (ESD) protection scheme for differential low-noise amplifier (LNA) was proposed in this paper. The new ESD protection scheme, which evolved from the conventional double-diode ESD protection scheme without adding any extra device, was realized with cross-coupled silicon-controlled rectifier (SCR). With the new ESD protection scheme, the pin-to-pin ESD robustness can be...
Two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional...
Wire bond reliability testing typically consists of aging bonds in a high temperature environment for long time periods, removing samples at intervals to assess bond shear strength and characterize the bond cross sections. In this way, the degradation of the bond can be monitored at discrete time intervals, and it is determined whether the bond will be reliable under long term operation at lower temperatures...
A 3D integration scheme for integrating a state-of-the-art CMOS IC with an arbitrary MEMS/sensor chip is reported. The integration scheme consists of a CMOS IC and a MEMS chip stacked on top of each other with the electrical interconnections between the chips being made using mechanically flexible interconnects (MFIs). In order to expose the MEMS/sensor device to the environment for sensing, the back...
This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4-21.5dBm of output power with drain efficiencies and power-added efficiencies of 56-64% and 46-51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V,...
This paper presents a process qualification and characterization strategy that can extend the foundry process reliability potential to meet specific automotive mission profile requirements. In this case study, data and analyses are provided that lead to sufficient confidence for pushing the allowed mission profile envelope of a process towards more aggressive (automotive) applications.
In this work we present the time dependent dielectric breakdown (TDDB) characteristics of LaO capped HfO2 layers with an equivalent oxide thickness of 8Å̊. The layers show maximum operating voltages in excess of 1 V. Such high reliability can be attributed to very high Weibull slopes. We examine the origin of the high slopes by a detailed study of the evolution of the stress induced leakage current...
Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using...
The impact of relaxation and droops in determining the voltage dependence of NBTI during product stressing is discussed. This has implications on the Fmax and Vmin guardbands extrapolated from product stress to use conditions. Voltage dependence for the shift of the 3sigma tail bits in both new and old technology nodes are compared to illustrate the importance of relaxation and droops.
We present results of a comprehensive reliability evaluation of a 2T-2C, 4Mb, Ferroelectric Random Access Memory embedded within a standard 130nm, 5LM Cu CMOS platform. Wear-out free endurance to 5.4 × 1013 cycles and data retention equivalent of 10 years at 85°C is demonstrated. The results show that the technology can be used in a wide range of applications including embedded processing.
Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and...
The effects of dc hot carrier stress on the characteristics of 60GHz power amplifiers on CMOS 65nm are investigated. The increase in the threshold voltage, the decrease in the transconductance and the output conductance of the MOSFETs caused by hot carriers leads to a loss performances of the PAs. A reliability study is first made on a 1 stage PA to validate the ageing model and the degradation explanation...
In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor...
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