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We present a dataflow based performance estimation and synthesis framework that will help hardware designers quantify the algorithm performance and synthesize their HW designs onto Field Programmable Gate Arrays (FPGAs). Typically, Digital Signal Processing (DSP) systems are designed by making gradual architectural choices in HW refinement steps. These decisions are based on performance quantification...
As part of the development of the High Granularity Calorimeter for the CMS Endcap at HL-LHC, The CMS collaboration is conducting a comprehensive series of beam tests. The first beam test, with a single HGC module was carried out in March of 2016 at the Fermilab Test Beam Facility, continuing to a 16 module test in July of 2016. We describe here the development of a low cost readout system that is...
In order to comprehensively evaluate and improve the performance of the Rogowski coil electronic current transformer (RCECT), this paper presents a method for steady state characteristic and the dynamic characteristic test. The testing scenario is configured in an electromagnetic transient simulation software (PSCAD), then the digital signals are reproduced as analog signals by amplifiers. The sensor...
In this paper, a new hardware/software design and implementation of an Induction Machine (IM) drive control topology is presented. Power electronic applications such as three-phase inverter require highly accurate switching frequency. This design uses a System on Chip (SoC) approach and implemented on a Field Programmable Gate Array (FPGA). The on-chip processor is used for high level programing while...
The biometric encryption system is a significant addition in the areas of privacy, security and convenience among its users. The intent of this research is to propose an RSA based biometric encryption system which can be realized on field programmable gate arrays (FPGAs) using hardware-software co-design methods. Due to the high number of hackers that stand to profit from sub-par security methods,...
Hadoop is an emerging data application for the big data processing. In Hadoop system, data compression is a significant part in processing big data effectively. Achieving this in software requires significant compute processing. In this paper we present the detailed design of a hardware compression accelerators. We also measure the performance of the hardware accelerators. Our analysis shows that...
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has...
Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing...
Autonomous mobile robots require high-performance computation to meet variety of requirements of functions, such as sensing, intelligent image processing and controlling actuators. We focus on FPGA as a hardware platform for autonomous mobile robot system. However, a FPGA-based system is not effective in development cost, since it requires HDL-based design whose productivity is relatively low. In...
In high-quality education, topics concerning the behavior and control of electrical machines and power electronics have to be taught not only theoretically but also in a practical manner. Hard- and software tools are necessary to fulfil this obligation. Nevertheless, commercial systems partially lack of functionality or full accessibility to implement custom solutions, which is obligatory in the research...
Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is...
The paper introduces a new multi-core SoC platform designed for industrial automation applications with mixed criticality. The applications are written in SystemJ language. The multi-core platform consisting of three different types of cores is implemented in a SoC that contains a standard dual-core ARM and a FPGA, which is used to run the critical part of the system. The platform is fully customizable...
This paper describes the design and characterization of a safety critical module for Eurobalise railway signalling. The design of the module is done on a HW/SW platform to include compliance to the safety regulations both at HW and SW level. The safety of the obtained design implemented on FPGA is then characterized through a fault injection campaign. The fault injection campaign isolated some corner...
Disturbances occurring on voltage signals following switching events or faults on power systems are defined as power quality problem. Power quality problems result in significant financial losses in the power systems in addition to faulty operation or breakdown of sensitive loads connected to the power system. Therefore, power quality problems should be swiftly detected and eliminated. This paper...
Embedded Systems Design primarily focuses on three hardware platforms namely Microcontroller, Digital Signal Processor and Field Programmable Gate Array. The competency gained in Microcontroller based design can be utilized in control structures design predominantly implemented as sequential structure for example state machines. FPGA applications usually require a combination of parallel and sequential...
This paper presents a random fault injector for CAN network. The injector is capable of generating errors in the CAN bus from the send of a sequence bits that violate operational rules of the CAN protocol. The injector was implemented and validated successfully. Finally, an experimental study of a CAN network was developed to examine the impact of faults in the worst case response time of messages.
Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable...
Hashing is an essential part of many database operators, such as joins or aggregation, especially when executed in parallel. Often, database engines resort to using easily computed hash functions like modulo to prevent that hashing becomes a bottleneck. The disadvantage of simple hash functions is that they produce imperfect data distributions, particularly when the data is skewed. Robust hash functions...
This paper presents a framework for hardware and software co-design to building systems designed to driver assistant using computer vision. This work is part of a doctoral research project nearing completion. To validate the model, a modular pedestrian detection is implemented by comparing the results obtained with other design.
Adaptive radiotherapy is a technique intended to increase the accuracy of radiotherapy. Currently, it is not clinically feasible due to the time required to process the images of patient anatomy. Hardware acceleration of image processing algorithms may allow them to be carried out in a clinically acceptable timeframe. This paper presents the experiences encountered using high-level synthesis tools...
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