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The Future Internet is expected to support services in both existing and new scenarios, in terms of mobility, quality, scalability and security, among other. In this work we present how Reconfigurable Computing (RC) may contribute to build Future Internet (FI) flexibility and security. Therefore, we discuss some aspects of FI initiatives which can be addressed by Reconfigurable Computing. Then we...
Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. Introduction to SDSoC: The Zynq SoCs and MPSoCs are natural fit for design teams consisting of software and FPGA hardware engineers. Teams with limited or no hardware resources however have been challenged due to the RTL (VHDL or Verilog) development expertise needed to...
High-level synthesis (HLS) promises to increase designer productivity in the face of increasing field-programmable gate array sizes, and broaden the market of use, allowing software designers to reap the benefits of hardware implementation. One roadblock to HLS adoption is the lack of an in-system debugging infrastructure. Although designers can run their software code on a workstation, or simulate...
In access-network-chip testing and verification, problems occur mostly on I2C control interface because of its complicated protocol and high requirement on reliability, using an automated testing tool with simple operation and high testing coverage could ensure the quality of chip as well as shorten the chip development cycle. The paper designs an automated system based on 5SGXEA7N2F45C2 FPGA chip...
A new implementation of LCX fault detection system based on the linear sweep frequency is presented in this paper. Firstly, the necessity and feasibility of fault detection for the LCX are illustrated, and detection system is elaborated form host software, FPGA design and synthesizer and chips control three primary aspects. Based on the demand and theoretical analysis, the LCX fault detection system...
FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods...
Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on...
FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. The Hastlayer project aims to give a tool to software developers familiar with the .NET platform to automatically transform performance-critical parts of their programs into seamlessly usable FPGA-implemented hardware, potentially yielding faster program execution...
This paper presents the design of RISC architecture based multicore processor using the Xilinx® development platform for designing and Spartan-6 FPGA for the implementation of the architecture. The light weight multithreaded kernel module is implemented on the top of the architecture to demonstrate the parallel programming potentials on the same. A task assigned to the processor is managed by the...
The template matching is an important technique used in pattern recognition. It aims at finding a given pattern within a frame sequence. Pearson's Correlation Coefficient (PCC) is widely used to evaluate the similarity of two images. This coefficient is computed for each image pixel, which entails a computationally very expensive process. This paper proposes an implementation of the template matching...
In the HEVC standard, motion estimation is one of the most complex task of the video encoder, requiring a great percentage of the encoding time mainly due to (a) a large set of Coding Tree Unit partitioning modes, (b) the presence of multiple reference frames, and (c) the varying size of Coding Units in comparison with its predecessor H264/AVC. In addition, HEVC adopts Variable Block Size Motion Estimation...
One of the consequence of the scaling down of latest technologies, is that digital circuits are more prone to be affected by faults caused by physical manufacturing defects, environmental perturbations (e.g., radiations, electromagnetic interference), or aging-related phenomena. Understanding the behavior of the whole system in the presence of faults affecting digital circuits is crucial for designing...
This work presents the development of a remote laboratory service and its application during the teaching of Control Systems subject of third course in a Telecommunication Technology and Service Engineering degree. The application was successful allowing the student to control the same components as remotely, in a similar way as they were in the laboratory. There was an elevated interest by the students,...
In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs. In Vivado HLS, the designer has the opportunity to employ libraries similar to OpenCV, a library that is well-known and wide used by software designers. The algorithms are compared in terms of area resources in two conditions: using the libraries and not using...
Algorithms for data encryption are one of the most important parts of modern communication systems. In this paper the results of hardware implementation of AES256 and TDES algorithms are presented. AES256 and TDES are implemented as an IP core with AXI interface because of constant growth of data transfer requirements in modern embedded systems, in order to improve their capability. Beside details...
The secrecy of information predominantly relies on secrecy of used cryptographic key rather than secrecy of cryptographic algorithm. Thus, a very important component of cryptographic system verification is proofing that cipher text originates from given plain text and specified cryptographic key. The implementation of such methodology is complex in bulk mode transmission systems with multi Gbit/s...
SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which...
NoC based SoC FPGAs are a promising technology for high performance embedded systems because they provide a good balance between performance, rapid time to market, cost and flexibility. The reconfigurability aspect of FPGAs allows FPGA platforms to adapt themselves to the various processing requirement of applications. On the other hand, many applications are designed in such a way that their quality...
The aim of this paper is to summarize the Work in Progress related to the design of a Collaborative Robotic Educational Tool. This tool arises to improve STEM (Science, Technology, Engineering and Math) educational programs for school students. The design is intended to cover different specifications such as: scalability, modular capabilities, reconfiguration possibilities and compatibility with the...
This paper presents the flexibility of technology FPGA in the implementation of automatic control systems. A digital structure at level hardware of a regulator of PI action was designed and built by the VHDL standard. Also, a Java graphical interface was developed for monitoring and control. Experiments were performed on a mechanism for position control consisting of DC motors with encoder, checking...
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