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The paper presents a high performance implementation of Fast Fourier Transform (FFT) algorithm using the notion of Hardware Software Partitioning. The co-design methodology was used to achieve higher system performance and design flexibility. The algorithm was originally implemented on a microcontroller (Atmegal6) but suffered from high execution delay. A low cost reconfigurable device like Spartan-3E...
The Fast Fourier Transform is one of the most widely used digital signal processing algorithms. It is used to compute the Discrete Fourier Transform and its inverse. As a result, these are widely used for many applications in engineering, science, and mathematics which include areas such as: communications, signal processing, instrumentation, biomedical engineering, numerical methods, sonics and acoustics,...
Because of their lower complexity and better error performance over K-best detectors, lattice-reduction (LR)-aided K-best detectors have recently proposed for large-scale multiinput multi-output (MIMO) detection. Among existing LR-aided K-best detectors, complex LR-aided K-best detector is more attractive compared to its real counterpart due to its potential lower latency and resources. However, one...
Automatic Number Plate Recognition (ANPR) systems have become one of the most important components in the current Intelligent Transportation Systems (ITS). In this paper, a FPGA implementation of a complete ANPR system which consists of Number Plate Localisation (NPL), Character Segmentation (CS), and Optical Character Recognition (OCR) is presented. The Mentor Graphics RC240 FPGA development board...
Conventional orthogonal frequency division multiplexing (OFDM) communication systems are typically designed assuming additive white Gaussian noise and interference statistics. However, in many applications, such as Wi-Fi and powerline communications (PLC), impulsive statistics are often observed. Impulsive noise can degrade the signal-to-noise ratio (SNR) of all subcarriers and impair communication...
Discrete Cosine Transform (DCT) plays a significant role in digital signal processing, especially in various international compressing standards, such as JPEG (Joint Photographic Experts Group), MPEG4 (Moving Pictures Expert Group), and H26X. Due to its high computational complexity, fast DCT algorithms have been widely studied in recent years. This paper highlights a novel approach to calculate DCT...
Altera's and Terasic's FPGA based (Hardware) Image Analyzer-Synthesizer (HIMANSY) is presented. The present tool has been used for both analysis and synthesis of images using the rotation angles based discrete orthogonal transforms. HIMANSY is equipped with video camera, DE2/DE3 Development Kit and LCD display. The core of the tool is based on the embedded NIOS II processor. The prototyping of novel...
The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in digital signal processing and communication systems. Radix-2 FFT algorithm is the simplest and most common form of the Cooley-Tukey algorithm. Radix-22 FFT algorithm is an attractive algorithm having same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm...
Efficient partitioning of hardware and software is essential for an optimized system design with a reduced development time. A reconfigurable Ultrasonic System-on-Chip Hardware (RUSH) platform has been developed to allow flexibility in system development for real-time ultrasonic signal processing applications via hardware-software (HW/SW) co-design. In this paper, we analyze how the various components...
High-speed implementations of computationally-intensive algorithms are essential for real-time ultrasonic signal processing application development. Hardware-software co-design allows flexible system development to carry out such experiments. In this paper, we developed a reconfigurable ultrasonic system-on-chip hardware (RUSH) platform which offers a Linux based development environment by integrating...
In this paper, we present a high performance adaptive FIR filter hardware architecture. In particular, the RLS (Recursive Least Square) algorithm for adaptive signal processing is explored based on QR decomposition, which is accomplished by using the Givens Rotation algorithm. The Givens Rotation algorithm is implemented using a systolic array and LUT-based Newton's method. This architecture is suitable...
Ultrasonic systems are widely used in industrial and medical imaging applications for diagnosis, nondestructive evaluation (NDE), defect recognition and classification. These applications require large amounts of data to be processed in real-time using computationally-intensive signal processing algorithms. In this study, we developed a Reconfigurable Ultrasonic System-on-Chip Hardware (RUSH) platform...
Abstract-This paper addresses the real-time demand of radix-4 FFT processor in modern digital signal processing domain. Full parallel and pipelined architecture can be a good solution while too much hardware is consumed. Therefore a useful optimization method of complex multiplier and twiddle factor which has been successfully used to implement the FFT algorithms achieving a reduction in multipliers'...
This work discusses a scalable hardware implementation of the Pease FFT algorithm, in which structural regularity from the Kronecker formulation is exploited to perform a complete folding of the transform. An address generator approach is proposed for both data permutation and phase factor scheduling throughout the stages. In this article we briefly review the Pease algorithm in Kronecker products,...
In this paper, we present a Reconfigurable Ultrasonic System-on-Chip Hardware (RUSH) platform for real-time signal analysis and image processing. The platform is designed to directly process the full range of ultrasound from 20 KHz to 20 MHz. The project aims to make it simple to effectively develop and implement algorithms in embedded software and reconfigurable hardware. This provides the user with...
This paper analyzes the gray projection motion vector estimation algorithm to illustrate the application environment and the characteristics of this algorithm, Indicate the needed of resources when implemented in hardware circuitry. Point at the Characteristics of the algorithm we made the corresponding optimized to make it more suitable for the hardware calculation. We design the corresponding circuit...
As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively...
Design and evaluation of a CORDIC (COordinate Rotation DIgital Computer) algorithm for a floating-point division operation is presented in this paper. In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation result. A hardware architecture of CORDIC...
This paper describes the arithmetic principle and discipline of FFT, analyzes rotation factor and data address of the node. It adopts flexible Verilog HDL to design and realize the data address unit of FFT implementation which is 64-point by radix-2. It uses Alter a company's PLD software Quartus II 8.0 (32-Bit) to compile and form top-level entity.
A compact RISC/FPGA based hardware architecture for high resolution SAR signal processing is presented. Sensor data rates above 300 Mbit/s and image dimensions of 8k × 4k pixels are processed in real-time. A maximum power consumption of less than 16 W enables for usage on small UAVs.
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