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This paper investigates gate driver design challenges encountered due to the fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate...
Logic gates for ultra-low voltages suffer from speed and robustness degradations, which are highly associated with the process technology. In this work a methodology for the automated design-space exploration of standard logic gates for a 28 nm FD-SOI technology is shown. Comprehensive design space explorations of inverter and nand2 gates show the benefits of back-biasing at sub-threshold supply voltages...
Data processing performed by adder circuits need to achieve low delay and low power at the same time while maintaining low cost, due to the steep growth in mobile computation devices. Recently proposed 1-bit full adder design that hybridizes transmission gates (TG) and standard CMOS offers significant PDP improvement. Two full adder implementations are presented in this paper which further optimizes...
Wide bandgap (WBG) power electronic devices realized using silicon carbide(SiC) and gallium nitride (GaN) are increasingly replacing their silicon(Si) counterparts in power electronics applications. The obvious advantages of these devices with their higher switching speeds, lower on state resistance and high temperature operation over Si devices have aided in the paradigm shift towards wide bandgap...
An analysis of the failure modes due to short circuit on planar and trench 1200ν — 40mΩ SiC-MOSFETs is presented, including single and multiple events. Short circuit waveforms, energy, as well as electro-thermal simulations are presented, enabling the identification of the main root causes of failure. Results demonstrate similar performance regarding failure after turn-off (thermal runaway, gate)...
In this paper different gate drive concepts to eliminate parasitic turn-on for SiC MOSFETs are discussed. Experimental results show a potential for lowering switching losses of SiC MOSFETs during fast switching operation, reduction of turn-off overvoltage across the bodydiode. Finally increased requirement on the gate drive unit are discussed.
This contribution investigates behavioral MOSFET models used for the simulation of conducted and radiated electromagnetic interferences (EMI) of an automotive inverter. A combined simulation of an equivalent circuit and the 3D geometry for a traction inverter based on 1.2 kV, 40 A SiC MOSFETs is presented. The model considers the MOSFET as a combination of parasitic elements of the package, voltage-dependent...
In recent years, the advent of Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) rank as one of the most significant development in power electronics. Its ability to work at high-voltage and high-frequency make MOSFETs become the most important electronic device for many power system circuit. For harsh environment application in example the satellite system, requires the MOSFETs dealing...
This paper deals with the optimized application of low voltage power MOSFETs in high frequency LLC DC-DC converter as synchronous rectification switches. The used semiconductor devices are trench MOSFET with improved figure of merit (FOM). The value of such a quantity is a good indicator that the MOSFET devices can operate at both high switching speed and extended current capability, as they are required...
Several high-voltage silicon carbide (SiC) devices have been demonstrated over the past few years, and the latest-generation devices are showing even faster switching, and greater current densities. However, there are no commercial gate drivers that are suitable for these high-voltage, high-speed devices. Consequently, there has been a great research effort into the development of gate drivers for...
This paper reviews existing reset schemes for the Muller C-element, one of the main primitives in asynchronous paradigms. Using a mathematical-based method and with the help of pass-transistor logic, an efficient implementation is developed that yields better performance. Simulations with a standard IBM 130-nm CMOS process, confirm that the proposed design achieves substantial improvement over existing...
Memristor is considered as one of the promising solutions to the fundamental limitations of the VLSI systems. Logic implementation with memristor device by considering its compatibility with CMOS fabric provides a new vision for digital logic circuits. This work presents a 2 by 2 multiplier cell design using a hybrid CMOS-memristor universal gate. The universal gate based implementation approach is...
In this paper, we explain the THz detection mechanism in sub-threshold Si MOSFETs by exploiting the exponential dependence of channel electron density to the gate-source voltage. According to our theory, this high frequency non-linear dependence is the underlying mechanism for rectification of THz radiation. The maximum detection frequency is limited by dielectric relaxation time of the electrons...
A 3-Dimensional (3D) strained Silicon Nanowire MOSFET simulation and inversion charge model are presented. The simulation studies are conducted based on electrical parameters of nanowires such as current and threshold voltage using a ATLAS TCAD simulator. The inversion charge model with Germanium fraction is formulated using a unified charge model. These characterization studies are performed to investigate...
An aggressive controlling for layout pattern density is becoming essential for the manufacturability of advanced processes. Focusing on analog layout under severe density constraints, this paper provides a novel idea that layout generation and verification are co-working on a density-aware format. Our idea follows a transistor-array(TA)-style of analog layout where unit-transistors of the same channel-size...
This work introduces a charge recovery comparator circuit for low-power, low-frequency applications. For the first time, the principles of charge recovery logic, or adiabatic logic, are applied to an analog circuit. The comparator is designed and simulated in a 180 nm technology and compared to state of the art solutions. Post-extraction simulations show that the proposed comparator consumes only...
The paper describes evaluation of the first, second and (with most attention to) third harmonics of the drain current in a MOS transistor operating in moderate inversion. The dependence of this current on the gate-source voltage is approximated using a simplified “reconciliation” model developed by Y. Tsividis. Then, the drain current components depending exponentially on normalized signal voltage...
An alternative electrical model for Ion-Sensitive Field-Effect Transistor (ISFET) sensors is presented in this work. The proposed model is worth to be employed in both DC and transient simulations where the behavior of the ISFET sensor coupled to its readout circuit can therefore be investigated. Whereas, previous models found in the literature could only be employed to perform DC simulations. The...
Ordinary single phase inverter gives a square wave output which when applied to electrical appliances may damage the later, reduce its efficiency as well as life as this inverter output waveform is not sinusoidal and contains lower and higher order harmonics in addition to fundamental. Moreover, the output voltage cannot be controlled. In this paper a single phase half bridge inverter is discussed...
A new technique of Ripple carry adder using majority gate based CMOS output wired logic is implemented. The ripple carry adder consists of four Full adder blocks. The carry from each stage is fed to the next stage as carry input. The Sum and carry outputs are obtained using output wired CMOS logic based majority gate. The number of transistors used in the proposed circuit design is less as compared...
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