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A novel method called SNEM (full S-parameter synthesis from near-end measurement) is proposed to obtain the full S-parameter matrix by probing only a subset of all the ports of a passive linear network. Other ports that are not probed need to be terminated by various impedance values. A termination error correction algorithm and a guideline for choosing termination impedance values have also been...
In this paper, a novel design for a test application board connection method is presented with its signal integrity analysis and optimization. The objective of the optimization is to support over 30 Gbps data rates with very high signal integrity performance and mechanical flexibility. The full channel includes a test board, connectors, cables and an interposer connecting components together. This...
This paper studies the period jitter of CPU Bclock on a multi-board cabled server platform. The channel output signal is computed with linear superposition method to reduce run time compared to the step response SPICE transient simulation. The average clock period as well as the standard deviation of ten thousand unit intervals (UIs) were calculated. Output Pj at the clock buffer or chip receiver...
Common mode signals on flexible cables often cause unwanted EMI. Common mode currents can be controlled by applying electromagnetic absorbing materials to the flexible cables. This work presents a set of specially designed test apparatuses that allow the performance of absorbing materials to be estimated for three typical structures known to radiate: monopole antennas, loop antennas, and transmission...
A new technique for frequency-domain compliance testing of high-speed differential interfaces is implemented in a signal integrity simulation tool that can accurately predict a channel's bit-error rate (BER) from seven frequency-domain parameters. This greatly increases the speed and efficiency of designing the number of computer systems required for custom configurations in scale-out data centers...
This paper describes the development of a calibration kit for measuring the scattering parameters (S-parameters) of balanced devices on a printed circuit board (PCB) substrate as well as the estimated uncertainty up to 25 GHz. The calibration kit is composed of a thru, reflect and a set of transmission lines to calibrate a Vector Network Analyzer (VNA) using the Thru Reflect Line (TRL) calibration...
This paper introduces a novel transmission line structure that can be employed in high-speed high-density copper interconnects, including both cables and connectors. The proposed structure uses a unique combination of dielectric materials with high and low permittivity values to decouple metal shields from adjacent signal pairs. In addition, the proposed structure employs an absorbing material to...
The partial fraction form of linear time‐invariant system transfer function is characterized through a cellular perspective, where each pole/residue fraction term is transformed into an equivalent circuit branch via an exact transformation. Minimal expressions for transformation of partial fraction form to/from equivalent circuit form are provided. The time‐domain and frequency‐domain impedance and...
The effects of geometry modulation applied to a periodic structure built in stripline technology are assessed by means of the dispersion diagrams calculated in the spectral, or k, plane by using a commercial electromagnetic eigenmode solver. Modifications of surfaces representing propagation modes, of electromagnetic band-gaps and of group velocities of Bloch waves following geometry modulation are...
Due to the increasing interest in Global Navigation Satellite Systems (GNSSs) for safety-critical applications, one of the major challenges to be solved is the provision of integrity to urban environments. In the past years, it has been noted that to do so, the integrity of the received signal must be analyzed with the aim of detecting any local effect disturbing the GNSS signal. Moreover, the detection...
In this paper, an optimization method using Particle Swarm Optimization (PSO) is proposed for the power/ground (P/G) pin assignment of large-scale high-pin-count ball grid array (BGA) packages. A general PSO working flow is introduced, and two examples of P/G pin assignment using the proposed method are presented. For validation, a comparison between Xilinx product and the result from PSO is presented...
In this paper, a package P/G pins assignment optimization method based on simulated annealing (SA) is proposed. Two objective functions describing power integrity (PI) and signal integrity (SI) are introduced. The basic flow of SA is presented, with the redefinition of the neighborhood of solution in SA, which ensures the feasibility in iteration. A 49×49 pinout example generated by the proposed SA...
The ability to accurately simulate and model Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) memory channels before an actual system is fabricated is an important requirement in early phase chip-package-board co-design to derive preliminary design feasibility information. Subsequently, there is a need to validate these memory channel simulation results once the actual memory...
The purpose of this paper is to consider the impact of humidity and temperature on the electrical properties of printed circuit boards (PCBs). PCB base materials are glass reinforced thermosetting laminates using a variety of resin systems with different loss characteristics.
The far end crosstalk (FEXT) saturation of microstrip differential signal pair is investigated in this paper. It is found that coupled length, rise time of attack signal, spacing between differential signal pair and attack line, coupling level of differential line can significantly affect FEXT of differential noise which causes serious signal integrity issues. In the situation when the FEXT of differential...
This paper presents an area efficient 3-tap speculative Decision Feedback Equalizer (DFE) with a novel current-integrating summer for data self correction in standard CMOS 180nm technology node. The conventional first-tap speculative half-rate DFE is composed of four different paths, which have exactly same hardware. In this paper, a novel area efficient DFE is proposed where the four summers are...
This paper proposes a passive equalizer that works as a digital filter compensating a large ISI (inter-symbol interference) of 100 Gbps or faster signal on high-loss signal lines on silicon interposers. The equalizer, which discretizes input signal through multiple signal reflection, is implemented on a silicon interposer, without need for circuit area and power supply on LSI (large-scale integration)...
Predicting and optimizing the package electrical performance for high speed input/output (IO) design requires an accurate and robust modeling methodology. Such a methodology requires high fidelity representation of physical structures and accurate characterization of broadband frequency dependent material properties. In addition, a modeling to measurement correlation flow that can very accurately...
Electronic systems are exposed to stress conditions during their life cycle. Chemical substances such as moisture and acid are the major source of stresses. The chemical stress condition can induce chemical degradation of electronic components and interconnects including solder joints. Chemical degradation often leads to malfunctions of electronic systems, ultimately resulting in system failure. To...
In this paper, a vertical probe card design for wafer-level mobile application processor (AP) chip test is proposed under LPDDR4 channel specifications. The probe card consists of a probe head and a multi-layer ceramic (MLC) board, and it is designed to have signal and power integrity to guarantee the wafer-level AP chips to be operated at 3.2 Gbps of speed under 1.1 V of supply voltage. We proposed...
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