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A 2.5 Gbps clock-data recovery (CDR) circuit is designed in 0.18 um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5 GHz by SONET OC-48 while the CMU loop runs at 625 MHz.The power consumption is 25 mW. The jitter bandwidth is 5.6 MHz. The peaking is 2.67 dB. The VCO gain is 163 MHz/V with a tuning range of 390 MHz. The output data...
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