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Using the Xilinx Zynq SoC, this work extends previous work by analysing and quantifying the effects of various outer (L2) caching behaviors and memory ordering models on memory accesses from a hardware accelerator (HA) implemented in programmable logic (PL) and from one of two ARM Cortex A9 CPUs. Memory accesses to the L2 cache/external memory and onchip memory (OCM) are both considered. The HA is...
This paper presents a novel hardware-oriented stereo vision system based on 1-D cost aggregation. Many researchers have implemented hardware efficient stereo matching to realize real-time systems. However, such methods require a large amount of memory. We proposed a system that is based on a hardware-software hybrid architecture for memory reduction. It consisted of grayscale 1-D cost aggregation...
An optimized architecture is proposed for real-time automatic cloud detection system with Spectrum and Texture Analysis Combination (STAC) approach. The STAC approach is hard to be implemented in hardware, for the calculation of fractal dimension (FD) and angle second moments (ASM) of the approach consumes large computation time and hardware resources. By optimizing the calculation process of the...
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