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Floating-point arithmetic plays major role in computer systems. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction. Among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts namely Sign part, and Exponent part and Mantissa part...
Arithmetic logic unit (ALU) is an important part of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we describes 8-bit ALU using low power 11-transistor full adder (FA) and Gate diffusion input (GDI) based multiplexer. By using FA and multiplexer, we have reduced power and delay of 8-bit ALU as compare to existing design. All design were simulated...
The performance and efficiency of conventional carry skip adder structure is improved by employing increment and concatenation scheme. In the existing system the multiplier is used which consumes more power. Instead of using this structure that consists of AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) is used for skip logic. Further development in energy and speed can be achieved by the structures...
Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process one of them is array multiplier. array multiplier half adder have been used to sum the carry...
We consider a content delivery network where multiple servers are connected to multiple cache-enabled clients. Clients request their corresponding contents from the servers and servers collaboratively transmit packets to fulfill all the requests. It is assumed that some contents are stored in the caches in off-peak time of the network without knowing the actual requests, the so called cache content...
Arithmetic Logic Units are one of the vital unit in general purpose processors and major source of power dissipation. In this paper we have demonstrated an optimized Arithmetic and Logic Unit through the use of an optimized carry select adder. Carry select adders have been considered as the best in their category in terms of power and delay. In this context a full adder optimized in terms of power...
Adders are the basic building blocks of any processor or data path application. In adder design carry generation is the critical path. To reduce the power consumption of data path we need to reduce Area and number of transistors of the adder. Carry Select Adder is one of the fast adder used in many data path applications. In this paper Power consumption, area and delay of different carry select adders...
This paper presents the modification of existing prominent multipliers like Wallace multiplier and Truncated Multiplier in order to improvise them in terms of power and area. In the existing Wallace multiplier architecture, the Carry Save Adder is replaced with Modified Carry Save Adder (MCSA)and further the full adder in the MCSA is implemented using Multiplexer. Similarly the regular full adder...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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