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Most existing multiprocessor schedulability analysis assumes zero cost for preemptions and migrations. In order for those analysis to be correct, execution time estimations are often inflated by a certain (pessimistic) factor, leading to severe waste of computing resource. In this paper, a novel Global Earliest Deadline First (GEDF) schedulability test is proposed, where Cache-Related Preemption Delay...
Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which a processor resource may serve an incoming request, when its access is arbitrated using time-predictable policies such as round-robin or FIFO. We call this value upper-bound delay...
In a multi-core system with shared resources, the accesses to the shared resources from several cores may experience non-deterministic arbitration delay due to resource contention. Such delay should be considered conservatively in the worst case response time (WCRT) analysis of multi-core systems. Recently, several techniques have been proposed to account for arbitration delay for shared resource...
There is an increasing interest among real-time systems architects for multi- and many-core accelerated platforms. The main obstacle towards the adoption of such devices within industrial settings is related to the difficulties in tightly estimating the multiple interferences that may arise among the parallel components of the system. This in particular concerns concurrent accesses to shared memory...
The demand for more computing power in current real-time systems carries on the development and research on multicore devices. Especially for hard real-time applications, like an engine control system, the software needs to be distributed and scheduled effectively. These applications consist of many tasks, which communicate data among each other. Considering a multicore system, communication between...
Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET)...
The performance and power efficiency of multi-core processors are attractive features for safety-critical applications, as in avionics. But increased integration and average-case performance optimisations pose challenges when deploying them for such domains. In this paper we propose a novel approach to compute an is WCET considering variable access delays due to the concurrent use of shared resources...
In modern non-customized multicore architectures, computing cores commonly share large parts of the memory hierarchy. This paper presents a scheme for controlling the sharing of main memory among cores, respectively the concurrently executing real-time tasks. This is important for the following: concurrent memory accesses are served sequentially by the memory controller. As task execution stalls until...
Given that power is one of the biggest concerns of embedded systems, many devices have replaced DRAM with non-volatile Phase Change Memories (PCM). Some applications need to adhere to strict timing constraints and thus their temporal behavior must be analyzed before deploying them. Moreover, modern systems typically contain multiple cores, causing an application to incur significant delays due to...
The advent of multi- and many-core processors comes with new challenges and opportunities for the designer of embedded real-time applications. By using parallel programming techniques (e.g. OpenMP) software engineers can leverage from the available hardware parallelism and speed up the algorithms. The inherent redundancy of multi-core architectures can also be used to implement fault-tolerance by...
Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key role in system's performance and the tightness of the Worst-Case Execution Time (WCET) estimates.
The state-of-the-art embedded systems are adopting multicore processors as multicore architecture provides high performance and better supports for computation intensive applications. Although cache improves the overall performance, designing multicore embedded systems with multilevel caches is a great challenge. Caches make thermal constraint crucial; parallel thread execution difficult; and timing...
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