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We design a novel DRAM controller that bundles and executes memory requests of hard real-time applications in consecutive rounds based on their type to reduce read/write switching delay. At the same time, our controller provides a configurable, guaranteed bandwidth for soft real-time requests. We show that there is a fundamental trade-off between the latency guarantee for hard real-time requests and...
The model of the virtual router with static and dynamic reconfiguration of resources is developed. This model allows to create effective virtual device with optimal parameters (length of queue, management discipline for queue overflowing, the number of service devices and their modes) in order to provide the required level of QoS for all services. The use of virtual network devices in the existing...
In this document we implemented several digital and filtering techniques in real time using Xilinx Zynq-7010 FPGA To achieve this we use a high level programming language like NI LabView to generate the VHDL that will be recorded in the hardware. We expose the mathematic characteristics of each one of the effects and the impact in the processing of the audio signal. We also compare with those we obtained...
In this paper, an FPGA based FIFO with efficient memory management is proposed, which allows fast forwarding of real-time Ethernet frames. There are two main drawbacks of the existing FIFO implementations with respect to the buffering of Ethernet frames. Currentness of data is not guaranteed in case of buffer overflow because the new frames are dropped in this case. Furthermore, exhaustive resources...
Mixed-criticality systems have tasks with different criticality levels running on the same hardware platform. Today’s DRAM controllers cannot adequately satisfy the often conflicting requirements of tightly bounded worst-case latency for critical tasks and high performance for non-critical real-time tasks. We propose a DRAM memory controller that meets these requirements by using bank-aware address...
Qualitative online billing system performance is essential for cost-effective service providers. This paper presents the method of technical resources' distribution of the billing server based on the resource requirements of different types of service that takes into account the daily load statistics of different types of services and increases the revenue by providing an individual approach to services...
We introduce ROC, a Rank-switching, Open-row Controller for Double Data Rate Dynamic RAM (DDR DRAM). ROC is optimized for mixed-criticality multicore systems using modern DDR devices: compared to existing real-time memory controllers, it provides significantly lower worst case latency bounds for hard real-time tasks and supports throughput-oriented optimizations for soft real-time applications. The...
In this paper, we present a real-time embedded implementation of the binary masking algorithm, which has been shown to significantly improve speech-in-noise intelligibility. Our real-time implementation relies on a balance of parallel processing and hardware pipelining. We have tested and evaluated our implementation on a Spartan 3A FPGA. The measured latency was 8.5 ms . The highest measured improvement...
Given that power is one of the biggest concerns of embedded systems, many devices have replaced DRAM with non-volatile Phase Change Memories (PCM). Some applications need to adhere to strict timing constraints and thus their temporal behavior must be analyzed before deploying them. Moreover, modern systems typically contain multiple cores, causing an application to incur significant delays due to...
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