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Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a...
In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of...
We propose an asynchronous, decentralized algorithm for consensus optimization. The algorithm runs over a network of agents, where the agents perform local computation and communicate with neighbors. We design the algorithm so that the agents can compute and communicate independently at different times and for different durations. This reduces the waiting time for the slowest agent or longest communication...
For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
A new 1-bit full adder cell has been introduced in this paper. According to this approach body-biasing and semi domino logic both are used in a single full adder. Body-biasing technique is used to vary the threshold voltage to operate this adder at higher speed by allowing the faster gate switching. The important thing in this approach is that there is no requirement of any external circuitry for...
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance...
A multi-phase technique for speeding up the measurement of delays via sub-sampling is presented. Measurement of delays using the sub-sampling approach leads to a very simple system implementation, and also provides the opportunity of trading off between bandwidth and accuracy. Such a scheme becomes extremely attractive for deep sub-micron processes due to its highly-digital nature and the ability...
Deep sub micron designs are susceptible to huge variations, justifying the in-situ optimization of power consumption in SoCs and IPs. It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct operation. Accurate estimation of error rates is required to use recovery driven DVFS techniques such as slack optimization [1], [2]. Due to extra logic...
Today's electronic devices move drastically towards high speed design feature. The traditional D-flip flop is no longer suitable for designing shift registers because of its low-speed performance. Many different types of shift registers, such as Universal Shift registers, Serial In Serial Out, Serial In Parallel Out, Parallel In Parallel Out and Parallel In Serial Out have been developed. Also, there...
As supply voltage is reduced, a power constrained test clock can be sped up in spite of the increased delay of the circuit. However, a large reduction in voltage makes the operation structurally constrained, requiring the clock to slow down. We determine an optimum supply voltage that allows fastest clock speed for a given power limit. Examples show that the test time can be reduced by as much as...
Resetting flip flops in high speed clock domain across wide silicon area is a challenge due to significant delay variations between the clock and reset signals. In this paper, a novel method of transmitting Reset Through the Clock (RTC) tree is proposed. At the root of the clock tree, multiplexing circuit encodes reset as pulses of width smaller than clock pulses whereas in the non-reset mode it passes...
Design methodologies such as Razor [3,4] minimize power dissipation by slowing down circuits so as to eliminate timing slacks to the point where occasional timing errors are observed. The main challenge here is the design of efficient mechanisms to detect and recover from these infrequent errors without loss of functionality. We present a design for widely used Wallace multipliers where, because of...
In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives...
This paper presents a low power clock and data recovery (CDR) circuit for a wireless body sensor node. The proposed circuit interfaces the RF receiver output with the digital processing. It consumes 50nW at 100kbps. It uses a delay locked loop (DLL) that is calibrated in one-shot fashion to save power, locking over 18X faster than prior art. The proposed circuit is fabricated in a 0.13?m CMOS technology...
Testing of a system-on-chip (SoC) consists of a schedule of test sessions. In each session, a subset of cores of the SoC is tested such that the peak power consumption of each core as well as that of the entire SoC remain under specified limits. In this work, we assume that each test session can be assigned its own clock frequency and VDD, which are related through the critical path delay constraint...
The testing, verification and evaluation of wireless systems is an important but challenging endeavor. The most realistic method to test a wireless system is a field deployment. Unfortunately, this is not only expensive but also time consuming. In this paper, we present the design and implementation of a digital wireless channel emulator, which connects directly to a number of radios, and mimics the...
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