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In the paper it is presented a designing algorithm for decoding the data provided by a two-channel incremental encoder in order to identify the rotation direction. Such information is useful when monitoring the operation status of various driving devices found within a vehicle. The resulting digital circuit is implemented on a FPGA (Field-Programmable Gate Array), which can be easily included as a...
In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We...
Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on...
Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process. The method provides set of steps for decoder implementation. Field-Programmable Gate Arrays circuits are selected...
In satellite on-board computers, memories are one of the components that need protection against radiation. Their effects can cause several types of errors like: Single Event Upsets (SEUs) that affect a bit of memory, Multiple-Cell Upsets (MCU), which corrupt several bits, and Single Event Functional Interrupt (SEFI) in control circuits, which can cause malfunction of the entire memory chip. This...
In order to improve the throughput of error correction decoding for the high-performance solid-state drives (SSDs), a semi-parallel low-density parity-check (LDPC) decoding architecture is proposed in this paper. The circuit of the LDPC decoder which can be dynamically configured with bit rate and code length is implemented using the scheduling control flow mode of single instruction multiple data...
Internet of Things (loT) is network connected “Things” such as vehicles, buildings, embedded systems, sensors, as well as people. IoT enables these objects to collect and exchange data of interest to complete various tasks including patient health monitoring, environmental monitoring, system condition prognostics and prediction, smart grid, smart buildings, smart cities, and do on. Due to the large...
Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads...
In this invited paper, we describe a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that this class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10−15 for BPSK transmission. In addition,...
In this invited paper, both binary and nonbinary LDPC codes suitable for optical transmission systems are described. The corresponding FPGA implementation has been discussed as well. The use of adaptive LDPC coding to deal with time-varying optical channel conditions is described as well.
Path metric sorting unit of successive cancellation list (SCL) decoders for polar codes is the main concern in this paper. After reviewing existing sorting units in SCL decoders, we propose 2 new sorting schemes namely quick select (QS) based selection algorithm and simplified bitonic sorter (SBT), which exploit the special data dependency of path metrics in log-likelihood ratio based SCL decoding...
String matching hardware engines generally utilize Ternary Content Addressable Memories (TCAMs). Although TCAM-based solutions are fast, they are expensive and power hungry. This paper proposes a high-performance memory-less architecture for string matching called Split-Bucket. It offers a performance comparable to TCAM-based solutions. Moreover, it is reconfigurable and scalable to the size of the...
A bladder neuromodulation with a system controller and microstimulator is proposed. The system controller is used for transmitting the stimulating parameters with four functions: fetching, decoding, calculating, and outputting. The fetching circuit receives series parameters from a phase-shift keying demodulator. The decoding circuit decodes the data for the stimulus parameter. The calculating circuit...
This paper describes the design and implementation of an End-to-End digital wireless communication system (E2E) system on the Zynq-7000 Field Programmable Gate Array (FPGA) and Evaluation Development (Zed) Board with an Analog Devices AD9364 Wideband Transceiver from a model-based design system. Furthermore, the paper presents the design path to reconfigure the software controlled logic blocks for...
Partial reconfiguration (PR) of a reconfigurable fabric is typically performed at run-time at the level of a "frame" (the smallest independently reconfigurable unit). Large frames often cause many elements to be reconfigured unnecessarily, causing the partial reconfiguration time to increase. While reconfiguring a large number of small frames, reduces the number of configuration bits used,...
In this study, Layered Low Density Parity Check (LDPC) Decoder algorithm in Error Correction Codes is implemented on FPGA. Firstly, Layered LDPC Decoder algorithm is designed with floating point in MATLAB, then fixed point model is developed. By testing Floating and Fixed point designs, transmitted information that is deformed by AWGN model is corrected by decoding iteratively. After this step, fixed...
Polar code has become a major milestone in information theory field in recent times. Researchers are still observing more efficient encoding and decoding structures. In this study, a new WIB based structure is proposed which reduces the computational complexity of WIB introduced as an early termination method for BP polar decoder in literature. Both proposed and WIB methods are implemented with VHDL...
The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present...
This paper simplifies the chase decoding algorithm for TPC codes for a particular modulation scheme (BPSK). Without reducing the decoding performance, the multiplication of the new algorithm is 33% of the original algorithm. The access algorithm of receiving matrix [R] is also optimized, and the access time of receiving matrix [R] is reduced to 3%. Finally, the 800M bps TPC decoder was implemented...
Efficient implementation of non-linear activationfunctions is essential to the implementation of deep learningmodels on FPGAs. We introduce such an implementation basedon the Discrete Cosine Transform Interpolation Filter (DCTIF). The proposed interpolation architecture combines simple arithmeticoperations on the stored samples of the hyperbolic tangentfunction and on input data. It achieves almost...
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