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For the feature of "slim and light" in portable devices, stacked 3D-IC architecture was introduced in the advanced packaging techniques. The traditional FR-4 substrate was substituted by Si substrates. In general, the thickness of Si chip and substrates would be larger than 300 micron. However, silicon is rigid and has high resistance of deformation. Therefore, the thermal stress caused...
Based on the elastic-plastic model, two-dimensional finite element analysis was used to analyze the Air-Gap Cu interconnects thermal stress behaviors. Firstly, the stress evolution with the Air-Gap interconnect formation process steps was studied. Then, two Air-Gap types of Cu interconnects, with Air-Gap in the metal line level or extending to via level, combined with three different dielectrics were...
Popcorn failure in Hyperelastic-plastic electronic packages under thermal load and Moisture is studied. Using the theory of finite deformation, we obtain the analytical relation between void growth and the sum of the vapor pressure induced by moisture and thermal stress induced by heat mismatch. Numerical analyses show that the critical traction decreases with decreases of yield stress-shear modulus...
In this study, three examples of failure analyses of electronic packaging by using the finite element method are presented. These are: (1) the failures (delaminations) near the interface between the filled copper and the silicon and between the copper and the silicon dioxide dielectric of the TSV of a 3D system-in-package (SiP) due to the local thermal expansion mismatch between the silicon and the...
Low-k materials have been introduced in the backend interconnects since 90 nm node for advanced microelectronic products in order to reduce the RC delay. However, the fragile low-k layer is very sensitive to the thermal stress induced by the CTE (coefficient of thermal expansion) mismatch at metal/dielectric level as well as at die/package level. In the die/package interaction, the transition to lead-free...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
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