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Quaternary logic requires a dedicated comparator circuit besides the usual add/sub unit which may not be optimal due to several reasons. In this paper, we have thoroughly discussed various alternative expressions for equality operator which serves as the basis for quaternary comparator. Then we have derived the necessary equations for single qudit comparator and extended it to serial multi qudit comparator...
This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is based on a novel parallel-prefix algorithm which drastically reduces the switching activity of the internal nodes of the circuit. When implemented by using the ST 90nm-1V technology, the proposed 64-bit comparator exhibits an energy dissipation of only 0.77μW/MHz and a delay of 258ps. With respect to a...
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