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This paper describes a simple method to perform MAX-MIN applications on input signals. Several transmission gates and a precise voltage comparator with low power consumption is used in this architecture. The proposed architecture operates at very high frequencies up to 200 MHZ and dissipates only 330 muw of power and is implemented in 0.335 u standard tsmc CMOS process. This design has the advantage...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
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