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In this paper, we propose a simple and efficient two-stage list synchronizer for frame synchronization of low-density parity-check (LDPC) coded data transmitted over the additive white Gaussian noise (AWGN) channel. The proposed method uses both synchronization sequence and code constraints for frame synchronization. In the first stage, a list of the most likely frame starting positions is made using...
Video signal processing algorithms are characterized by high computational complexity and high memory throughput. Since the multicore architectures can provide high computational capacity and high throughput, they suit the video processing applications very well. However, it is very difficult to deal with the increasing design complexity and cost of the multicore system. For video processing application,...
In this paper, we propose a robust STBC transmission scheme to combat the timing synchronization errors over frequency-selective multiple-access channels. First, the equivalent channel model in the presence of timing synchronization errors is derived and we find that the synchronization errors result in an equivalent channel model with larger number of correlated channel taps. Based on this correlated...
Three applications in wireless networks where model-free stochastic learning is applicable, are discussed. The learning based optimization problems are formulated and simulation results are presented. Some open issues are also discussed.
The deadlock resolution problem can be informally stated as follows. There exists a set of actions, generated at different times, with some complex and contradictory precedence constraints between their executions. To resolve a deadlock, some of the actions need to be aborted; this enables to execute the remaining ones. This problem naturally arises in the context of distributed systems, e.g. communication...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
This paper develops a new distributed BFS algorithm for an asynchronous communication network. This paper presents two new BFS algorithms with improved communication complexity. The first algorithm has complexity O((E+V1.5)??logV) in communication and O(V1.5??logV) in time. The second algorithm uses the technique of the first recursively and achieves O(E??2 √logVloglogV) in communication and O(V??2√logVloglogV)...
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