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This paper describes a router which is the key component of a scalable asynchronous on-chip and inter-chip communication infrastructure for an application-specific parallel computing system. We use this system as a universal platform for real time simulations of large-scale neural networks. The communications router supports multiple routing algorithms, and is pipelined to boost its throughput. The...
Processor implementation and performance analysis are fundamental in computer architecture education. A processor can be described at different abstraction levels: a black box with inputs and outputs, the composition of RT (Register-Transfer) level components, the composition of gate level components, etc. Performance of a processor is impacted by factors such as clock cycle, programs, and componentspsila...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
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