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Process variations in integrated circuits have significant impact on their performance, leakage, and stability. This is particularly evident in large, regular, and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation...
High density 3D memory cell array using SGT(Surrounding Gate Transistor) on 3D IC is proposed. SGT with 4F2 cell size shows uniform cell characteristics with a low resistive bit-line path on 3D IC. Parasitic bit-line capacitance of the structure can also be much lower compared to conventional 2D memory cell array or SGT cell array on bulk substrate, which is especially good for memory feature size...
Program disturbance characteristics of 3D vertical NAND Flash cell array architecture have been investigated intensively. A new 'program Y disturbance' mode peculiar to 3D NAND Flash cell is defined. Swing characteristics of poly-Si channel and increased NOP (number of program) stress have been compared with 2D planar NAND Flash cell. In this paper, new program method pertinent to 3D NAND Flash memory...
A novel 3D flash cell array architecture, called "hybrid 3D", is proposed to provide the distinctive low address selection method of stacked channels, suitable for conventional NAND page operation. The strings are composed of GAA type selector and double gate type cells, and their key characters were verified independently. The GAA selectors showed excellent and uniform switching character,...
The dramatic market demand for flash memory in the past decade has vigorously driven technology evolution. Traditional memory scaling is facing huge lithographic barriers resulting in the inevitable pursuit of non-planar solutions. In this paper, we discuss the process technologies that are enabling us to overcome the challenges of extending the current planar platform while transitioning into future...
A novel PN diode decoding method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous 3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming...
For the past thirty years, the downscaling has been the guiding principle in the field of High-density semiconductor memories. However, recently, the limit of planar bulk MOSFETs is becoming apparent. Therefore, in order to extend the scalability of memory technology to the nano-scale generation, a new device structure is necessary. From the viewpoint, I will discuss future High density Memory with...
Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (~20 nm) and poly channel thickness (~10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F~2X nm node, and no penalty of increasing...
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