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The Multiple Signal Classification (MUSIC) algorithm is a powerful technique for determining the Direction of Arrival (DOA) of signals impinging on an antenna array. The algorithm is serial based, mathematically intensive, and requires substantial computing power to realize in real-time. Recently, multi-core processors are becoming more prevalent and affordable. The challenge of adapting existing...
The emergence of streaming multicore processors with multi-SIMD architectures and ultra-low power operation combined with real-time compute and I/O reconfigurability opens unprecedented opportunities for executing sophisticated signal processing algorithms faster and within a much lower energy budget. Here, we present an unconventional FFT implementation scheme for the IBM Cell, named transverse vectorization...
With the increasing number of cores integrated on a single chip, inter-core communication becomes more important in how to effectively support applications on multi-core platform. In this paper, we analyse the characteristics of multi-core tasks and classify processor cores into two categories based on their different functions: control core and computing core. According to the classification, we...
This paper presents the MIPA4k, a 64times64 cell mixed-mode image processor array chip. The processor cell includes an image sensor, A/D/A conversion, embedded digital and analog memories and hardware-optimized grayscale and binary processing cores. This paper presents the architecture of the processor cell and the different functional hardware. The processor has been manufactured in a 0.13 micron...
A study of two applications programmed using three models of varying complexity reveals that implicit management of locality can produce code with performance comparable to code generated from explicit management of locality.
The trend toward high processing power at a reasonable cost continues with the emergence of multi-core architectures with large number of cores. In such computing systems, a major technological challenge is to design the internal, on-chip communication network.This not only depends on high performance in latency, bandwidth, and fairness in contention under heavy loads, but also depends on an efficient...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
The contributions of special session deal with emulated digital CNN implementations based on tree different array processor architectures, namely Graphics Processing Units, IBM Cell processor and Xilinx FPGAs.
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
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