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Latch based arrays are commonly used as small embedded memories. There are often a large number of such memories in a design. Due to the large area overhead of memory BISTs, scan is often used to test such memories. In this paper we show that with a minor modification of a marching sequence targeting only the transition delay faults at the latch boundaries, a comprehensive set of faults can be detected...
This paper proposes a programmable Built-In Self-Test (BIST) approach for DRAM test and diagnosis. The proposed architecture suits well for embedded core testing as well as for stacked and stand-alone DRAMs and it provides programmability features for executing both March and NPSF-oriented test algorithms. The proposed BIST structure is designed to be easily customized with memory topology parameters...
Considering the physical layout, a comprehensive TCAM test scheme divides TCAM test into test for TCAM core and test for peripheral circuit. Besides, it schedules the existing test algorithms to develop an optimized test algorithm.
Dynamic cache resizing coupled with built in self test (BIST) is proposed to enhance yield of SRAM-based cache memory. BIST is used as part of the power-up sequence to identify the faulty memory addresses. Logic is added to prevent access to the identified locations, effectively reducing the cache size. Cache resizing approach can solve for as many faulty locations as the end user would like, while...
Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterativelogicarray (ILA) of processing elements (PEs) and multiplying elements (MULs). The functions of each processing element and multiplying elements are modified to be bijective to meet the M-testable conditions...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
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