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This paper presents a hybrid switch that parallels a power MOSFET and an IGBT as the main switch of a zero-voltage switching inverter. The combination features the MOSFET conducting in the low current region and the IGBT conducting in the high current region, and the soft switching avoids the reverse recovery problem during the device turn-on. A custom hybrid switch module has been developed for a...
Degradation and recovery of a multi-layer high-k SiGe pMOSFET due to the negative bias temperature instability (NBTI) is modeled on the basis of a refined non-radiative multi-phonon (NMP) theory. As the SiGe-layer forms a quantum-well inside the substrate, quantum mechanical effects like subbands are incorporated into the model. In combination with a distribution of defects featuring different energies,...
We have developed the compact IGBT model HiSIM-IGBT, based on a complete solution for the potential distribution, which connects the surface-potential of the MOS-FET part to the bipolar part by an iterative procedure in a self-consistent way. Here we report the self-heating extension of HiSIM-IGBT, a compact model for power diode including the reverse recovery effect and the model application to accurate...
A dual 1200 V, 400 A power module was built in a half-bridge configuration using 16 silicon-carbide (SiC) 0.56 cm2 DMOSFET die and 12 SiC 0.48 cm2 JBS diode die. The module included high temperature custom packaging and an integrated liquid cooled heat sink while conforming to the footprint and pinout of a commercial dual IGBT package. Die encapsulant was not used, to allow data collection by infrared...
The 5×4.2 mm2 chip of the SiC DIMOSFET was fabricated and tested. The drain-source avalanche breakdown voltage without any gate bias (Vgs=0V) is measured to be >1000V. The drain current (Id) >40A is observe under the conditions of Vds=1V and Vgs=+20V. Typical Ron and specific Ron are measured to be 22 mΩ and 3.5 mΩcm2 with Vth=2.3V. The SiC DIMOSFET is introduced into the PE circuits of the...
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
SiC power devices have very promising future because their ultra low conduction and switching losses and ability of working at high temperatures. SiC MOSFET not only has very low switching loss but also shows no degradation in Rdson at 150??C. In order to achieve ultra low switching loss for SiC BJT, a new drive method is proposed and implemented. These characteristics make SiC power MOSFET/BJT devices...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
A new, rugged 100 V power MOSFET of the OptiMOStrade 2-family is described. By applying compensation principles, a device technology was developed that combines low on-state resistance RON with outstanding switching properties. The technology also offers a small gate charge QG and a small gate resistance RG. In addition, the internal body diode, when acting as freewheeling diode, reveals a soft reverse-recovery...
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