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Recent technological advances allowed the word to construct several wearable products that can capture and process the human body bio-signals. The PPG signal becomes one of the most contenders in heart rate monitoring due to their prominent features, flexibility, effectiveness and low costs. This paper present a novel System of PPG Heart rate calculation based on FPGA, using the Pan and Tompkins as...
This paper reports on the Field-Programmable Gate Array (FPGA) real-time implementation of a vector control scheme, by means of hardware-in-the-loop simulation. This approach will be applied for a PMSM used to propel an electric scooter, preceding its integration in a more complex experimental setup. The emerging need for powerful, flexible system-on-a-chip (SoC) platforms for developing complex drive...
This paper describes and verifies a method of implementing bit error rate (BER) calculation for FPGA-based physical layer security techniques for Software Defined Radio (SDR). Specifically, we describe an independent source signal processing architecture for an efficient calculation of BER for wireless communication modules across the transmitter and receiver nodes. The source components at the transmitter...
Annotation — This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). The implementation...
Encoders using generator polynomials and linear-feedback shift registers are the key parts of communication technologies widely used in most of today's integrated as well as field systems. This paper presents a detailed comparison of three ways of implementation of configurable encoders arranged in PENCA and implemented in Xilinx and Altera FPGAs.
Failure tolerant data encoding and storage is of paramount importance for data centers, supercomputers, data transfers, and many aspects of information technology. Reed-Solomon failure erasure codes and their variants are the basis for many applications in this field. Efficient implementation of these codes is challenging because they require computations in Galois fields, which are not supported...
This paper presents a time-delay system which originally has chaotic behavior, yet lost that dynamic due to finite quantization levels of state variable representation. One method to overcome this destructive effect of digitalization is engaging a time-varying delay amount which is studied in this paper. Based on this system, random number generator (RNG) topologies are demonstrated with better throughput...
Miniaturized voltage sensors (electrodes) implanted into the brain tissue are capable of recording the brief electrical impulses (spikes) of neurons located close to the electrode sites. To investigate the activity of individual neurons and discriminate spikes generated by different neurons a technique called spike sorting can be applied on the recorded data. However, the performance of current spike...
In this study, by using bit error rate and signal to noise ratio performances, the analytical and experimental results of a chaotic on-off keying communication system are compared with each other. FPAA and FPGA implementations of chaotic digital communication system are presented with analytical ones.
BER (bit error rate) measurement is an important criterion to analyze digital communication systems. In literature this measurement generally performed through simulation programs like Matlab/Simulink. It is considered that the simulation programs may not represent a real communication system and also they are quite time consuming and expensive. However, modeling communication systems with parallel...
Digital Secret Unknown Cipher (SUC) has been proposed in the last decade targeting to counteract the drawbacks of the traditional analog Physical Unclonable Functions (PUF). The SUCs, as pure-digital units, exhibit consistent operation during the whole digital unit's lifetime. This makes SUCs as PUF alternatives attractive for practical creation of clone-resistant units for a broad spectrum of applications...
A new cryptosystem approach based on Lorenz chaotic systems is presented for secure data transmission. The system uses a stream cipher, in which the encryption key varies continuously. Furthermore one or more of the parameters of the Lorenz generator is controlled by an auxiliary chaotic generator for increased security. The system is implemented by using two separate Spartan 6 FPGA boards. Security...
This article, describes the implementation of QPSK modulator and FPGA programming aspects for carrier frequency control for data transmission units in space applications. The module occupies lesser area for integration, operates on lower power and supports higher data rates than conventional modulator units of Indian Space Research Organization (ISRO). The scope of a miniature and low power modulator...
This paper proposes a hardware architecture of the multi-band spectral subtraction method for real-time speech enhancement. The proposed hardware architecture has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG) and Nexys-4 development board. Multi-band approach is based on the fact the whole speech spectrum does not be affected uniformly by the colored...
This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array...
Latest researches related to Wide Area Measurement Systems (WAMS) recommends the development of a cost-effective FPGA based phasor measurement unit for developing a real time synchrophasor network. This paper presents an algorithm for an FPGA based Phasor Measurement Unit (PMU) modeled using Xilinx Vivado System Generator design suite. The backbone of the proposed PMU algorithm is the Non Recursive...
In this paper we describe the characteristics of four chaotic maps that are simulated by MATLAB to evaluate their entropy, bifurcation diagrams and Lyapunov exponent. From, the bifurcation diagrams, we choose values to search improved binary sequences using computer arithmetic of 32 bits in 2's complement and fixed point formats. In this manner, we choose the chaotic map with good entropy and positive...
Solar voltaic panels are getting common as a micro grid energy source day by day. Ample requirement of power quality improving devices are there in the grid. The scenario gives rise to a question that how we can avail more power quality improving devices, like static reactive power compensators by effective utilization of available devices. All the grid connected solar plants requires a three phase...
With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of...
In recent years, SRAM-based FPGAs have been applied in space due to its high density and configurability. However, due to its high sensitivity to SEU, it is difficult to be applied in space. With the decrease of the feature sizes, SRAM-based FPGAs are more sensitive to SEU. Therefore, how to evaluate the sensitivity of a design to SEU in FPGA is very important for the application in space. This paper...
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