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Multi-core architectures have become mainstream. Trends suggest that the number of cores integrated on a single chip will increase continuously. However, lock contention in operating systems can limit the parallel scalability on multi-cores so significantly that the speedup decreases with the increasing number of cores (thrashing). Although the phenomenon can be easily reproduced experimentally, most...
Parallelism is the most important mean to exploit the computation potential of multi-core processors. Real applications, particularly, commercial applications often have strong dependence that has to be respected. In order to achieve reasonably good performance, hybrid parallelism schemes usually need to be applied in these applications. Furthermore, parallel applications with task and pipeline parallelism...
Multi-core technology can provide valuable benefits for improving safety critical embedded systems. Examples range from multiple core architectures, introducing system redundancy, asymmetric multiprocessing allowing high software diversity, to hyper visors reducing system complexity. Can these benefits be taken for granted without considering the drawbacks and effects that come with them? The move...
Multi-core trends are becoming dominant, creating sophisticated and complicated cache structures. Also, the bigger shared level-2 (L2) caches are demanded for higher cache performance. One of the easiest ways to design cache memory for increased performance is to double the cache size. However, the big cache size is directly related to the area and power consumption. Especially in mobile processors,...
Numerous new issues appear as the single processer is developing towards the multi-core processor. The research on compiler-based heterogeneous multi-core structure is the one of the issues. Starting from the structure analysis, this paper explains the effective thread management by heterogeneous multi-core structure and thus demonstrates the advantages of the compiler-based heterogeneous multi-core...
It's a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. The Reconfigurable Logic is logically divided into Reconfigurable Processing Units (RPUs), which are coupled with General Purpose Cores (GPCs)...
Safety-critical system-of-systems need high dependability as failures can be catastrophic. Unfortunately, system dependability is sometimes sacrificed for cost, energy and performance reasons. This has been the case for the “time-triggered co-operative” (TTC) design methodology. Correct use of a TTC approach can guarantee a very high degree of reliability, robustness and predictability: incorrect...
The advent of multi-core processors has made parallel computing techniques mandatory on main stream systems. With the recent rise of hardware accelerators, hybrid parallelism adds yet another dimension of complexity to the process of software development. This article presents a tool for graphical program flow analysis of hardware accelerated parallel programs. It monitors the hybrid program execution...
Dynamic program execution monitors allow programmers to observe and verify an application while it is running. Instrumentation-based dynamic program monitors often incur significant performance overhead due to instrumentation. Special hardware supports have been proposed to reduce this overhead. However, these supports mostly target specific monitoring requirements and thus have limited applicability...
To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional...
Simulation of new multi- and many-core systems is becoming an increasingly large bottleneck in the design process. This paper presents the ACME design automation tool flow that facilitates the hardware emulation of newly proposed large multi-core interconnection networks on FPGAs to mitigate the slowdowns of single threaded event driven simulation. The tool is aimed at computer and network architects...
A recent trend in the design of commodity processors is the combination of multiple independent execution units on one chip. With the resulting increase of complexity and transistor count, it becomes more and more likely that a single execution unit on a processor gets faulty. In order to tackle this situation, we propose an architecture for dependable process management in chip-multiprocessing machines...
The relationship between the CPU and memory has always been of prime importance in the HPC ecosphere. Current trends in multi-core chip designs look to alarmingly upset the balance of that relationship. The number of CPUs in a chip is growing, while the interface to memory stays relatively static. How are we to adapt our software to this new paradigm in order to maximize the utility of those extra...
There are two problems emerged while multi-core platform become popular in daily life, no matter for high end or low end. The first is how to fully utilize computing resource of these cores without requirement of large modifications of current software design model. The second is about dividing a piece of serial program into parallel program. However, the latter is the responsibility of compiler,...
Processor manufacturers have turned from driving clock speed higher to building multi-core systems for improving performance. This paradigm shift by hardware manufacturers means that the software community can no longer count on advances in the hardware to improve application performance. The free lunch is indeed over, and mainstream developers now have to deal with issues of concurrency and parallel...
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