The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Verifying the execution of a parallel program against a given memory consistency model (memory consistency verification) is a crucial problem in the functional validation of Chip Multiprocessor (CMP). In the absence of additional information, the above problem is known to be NP-hard. By adopting the pending period information, this paper proposes the first linear-time software-based approach to memory...
Verifying the execution of a test program against the memory consistency model is known to be NP-hard. Because of lacking extra observability, verifying the memory consistency model in post-silicon stage is even harder than in pre-silicon stage. In this paper, by identifying the pending windows of microprocessor and introducing the resultant time order restrictions, we propose a low time complexity...
Recognizing the strategic importance of embedded computing for industry and society, the European Commission formed, together with industry, academia, and national governments, the European technology platform ARTEMIS (Advanced Research and Technology for Embedded Intelligence and Systems) in 2004. It is one goal of ARTEMIS to develop a cross-domain embedded system architecture, supported by design...
Executing sequential program on multi-core is crucial for accommodating instruction level parallelism (ILP) in chip multiprocessor (CMP) architecture. One widely used method of steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings much hardware complexity and area overhead. This paper presents the Global Register Alias...
Networks on Chip (NoCs) are considered to be the best candidate for the future on-chip communication of Chip Multiprocessors (CMPs). However, till date, general-purpose operating systems (OSs) for NoC-based CMP have not been examined. As the trend of NoC-based CMPs continues, OSs are required for the efficient use of NoC and for providing environment for general-purpose applications. In this study,...
This paper proposes a fast and efficient multi-processor architecture for devices a requiring high speed performance. The proposed method connects four basic processor modules (BPM) including CPU's in a pipeline shape to enhance execution speed. Also, using a specific BPM selectively regarding to multimedia applications increases the efficiency, and has more flexibility by software implementation...
Design-time application mapping is limited to a predefined set of applications and a static platform. Resource management at run-time is required to handle future changes in the application set, and to provide some degree of fault tolerance, due to imperfect production processes and wear of materials. This paper concerns resource allocation at run-time, allowing multiple real-time applications to...
Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainability improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections...
Due to the multi-processor nature of Network Processors (NP), data packets entering the system are processed in parallel and might be transmitted out-of-order at the output leading to a significant degradation in network performance. In this paper we propose a new well-structured, area-efficient, and high speed hardware architecture for packet re-sequencing. For this purpose, several buffering techniques...
Summary form only given. Inherent limitations on the computational power of sequential uniprocessor systems have led to the development of parallel multiprocessor systems. The two major issues in the formulation and design of parallel multiprocessor systems are algorithm design and architecture design. The parallel multiprocessor systems should be so designed so as to facilitate the design and implementation...
The introduction of high-performance applications such as multimedia applications into embedded systems led the manufacturers to provide embedded platforms able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor platforms. In this paper, we present...
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods in order to meet future design constraints. We believe one solution is to add a new design exploration step above current methods. This extension corresponds to an abstraction rising to provide designer with a restricted...
Nowadays, many high-speed Internet services and applications require high-speed multidimensional packet classification, but current high-speed classification often use expensive and power-slurping hardware (such as TCAM and FPGA). In this paper, we presented a novel algorithm, called AM-Trie (asymmetrical multi-bit Trie). Our algorithm creatively use redundant expression to reduce the height of Trie;...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.