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Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as...
This paper proposes a low complex hardware accelerator algorithmic modification for n-dimensional (nD) FastICA methodology based on Coordinate Rotation Digital Computer (CORDIC) to attain high computation speed. The most complex and time consuming update stage and convergence check required for computation of the nth weight vector are eliminated in the proposed methodology. Using the Gram-Schmidt...
Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain HDL codes from highlevel language functional descriptions. With high-level synthesis it becomes easier to design coprocessors, accelerators, and other special-purpose hardware. Nonetheless,...
Due to low masking-complexity property of the addition chain, it has been widely researched for evaluating the S-boxes in the recent literatures. This paper summarizes four main addition chains developed for the AES S-box in the existing literatures and chooses the most area-efficient addition chain. To further reduce the masking complexity, this paper proposes an improved algorithm for evaluating...
The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level of abstraction of design stages does not necessarily gives penalties in terms of performance or resources. Dataflow programs provide behavioral descriptions...
Electronic System Level (ESL) design flow tries to handle the complexity of today's System-on-Chip design and verification. Due to this complexity, design and verification methodologies start from an abstraction level higher than Register Transfer Level (RTL). In ESL, verification becomes a major bottleneck in the design flow, and finding a good verification methodology at this abstraction level is...
The complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware...
This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix −24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and...
The complexity of formalizing the semantics of Verilog is significant. This presents an impediment when attempting to provide high assurance in the correctness of Verilog synthesis. This paper explores the use of higher-order transformation as a paradigm for implementing a synthesis system for a small subset of Verilog. The resulting system is capable of synthesizing net lists in the Xilinx Net list...
We present an approach to verifying the codesign of software and hardware. Our approach verifies that a reference design, perhaps a straightforward software implementation, is equivalent to a design combining software and reconfigurable hardware, possibly using runtime reconfiguration. Our approach combines symbolic simulation with equivalence checking to compare symbolic output expressions. Whilst...
Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to...
Data process algorithms are increasing in complexity especially for image and video coding. Therefore, hardware development using directly hardware description languages (HDL) such as VHDL or Verilog is a difficult task. Current research axes in this context are introducing new methodologies to automate the generation of such descriptions. In our work we adopted a high level and target-independent...
A simplified hardware verification platform based on layered approach is implemented using SystemVerilog. SystemVerilog unifies several proven hardware design and verification languages in the form of extensions to Verilog HDL. The importance of a verification platform based on OOP technique is increasing for high-level functional verification. The proposed platform consists of components such as...
The increasing complexity in the design of protocol based sequential digital systems such as USB3.0 and PCI express (PCIe), is leading to an increased time to market constraint. This paper introduces a UML based visual design approach to address this increased complexity in the design of IP as well as System-on-Chips (SoC). A hardware development method for USB3.0 device using the Unified Modeling...
Turbo code is a class of convolutional codes which have great deal of interest as they attain the ultimate limits of the capacity of communication channel. They are known as ??The ultimate Error Control Codes?? which made them move rapidly from research laboratories to practical applications throughout the world. The use of these codes has been proposed for several applications where highly reliable...
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