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The computation of the arctangent of a complex number, i.e., the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In this brief, we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a first stage that performs a coarse approximation of the atan2 function and a second...
This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is based on an inverter, implemented as a combination of Parabolic Synthesis and second-degree interpolation, followed by a multiplier. It is implemented with and without pipeline stages individually and synthesized while targeting a Xilinx Ultrascale...
String matching hardware engines generally utilize Ternary Content Addressable Memories (TCAMs). Although TCAM-based solutions are fast, they are expensive and power hungry. This paper proposes a high-performance memory-less architecture for string matching called Split-Bucket. It offers a performance comparable to TCAM-based solutions. Moreover, it is reconfigurable and scalable to the size of the...
There is an increasing number of applications employing Self-Organizing Maps (SOM) for multidimensional categorization tasks. Those applications range from spoken- and written-word recognition and monitoring of industrial environments, to Internet of Things and image processing. SOM is a neural computing model with unsupervised learning, which is attractive for implementing embedded systems to operate...
In this work, a novel method Reduced CORDIC Based Logarithm Converter (RCBLC) is introduced for computing the specific-based logarithm of the binary values, and then the hardware architecture of RCBLC based on FPGA is analyzed in detail. Hardware architecture of RCBLC is implemented such that it enables logarithm conversion with both high output bit-sensitivity and low resource utilization. In addition...
In this paper, we present a new architecture forFPGA checkpointing along with an efficient mechanism. Wethen provide a static analysis of original HDL source code toreduce the cost of hardware for checkpointing functionality. Ourevaluations show that with the proposals, checkpointing hardwarecauses small degradation in maximum clock frequency (less than10%). The LUT overhead varies from 14.4% (Dijkstra)...
Originated from Chinese Remainder Theorem in the 4th century AD, Residue Number System (RNS) has been regarded as a promising number representation method in the field of digital computer arithmetic. Even though reconfigurable hardware devices such as Field Programmable Gate Arrays (FPGA) have been a popular platform for RNS applications due to its feasible architectural features, work that explores...
Digital signal processing techniques are widely used for a large number of applications with digital filters being considered as one of the basic elements. Digital filter design involves several multiply-and-accumulate (MAC) operations, which consume a large amount of hardware resources and computation cost. Distributed Arithmetic (DA) approach is proposed in literature as an alternative and efficient...
This paper presents the design of RISC architecture based multicore processor using the Xilinx® development platform for designing and Spartan-6 FPGA for the implementation of the architecture. The light weight multithreaded kernel module is implemented on the top of the architecture to demonstrate the parallel programming potentials on the same. A task assigned to the processor is managed by the...
With shrinking time to market for VLSI industry, there is a constant need for hardware — software codevelopment in the VLSI design flow. FPGAs and Emulation systems offer a great help to verification and validation engineers to achieve the same in the VLSI design flow. Further, to enable design verification engineers to create close to real chip scenarios and interface with external peripherals like...
This paper describes part of project that implemented the image processing of a CMOS sensor for endoscopic purposes. The sensor is a small sized device of 1×1mm2 and the image processing has been done inside a FPGA. This part of the work describes the implementation of the Gamma function with a balance between the resources needed and the accuracy. A linear piecewise solution was used that stores...
This paper proposes a FPGA based hardware architecture for quadruple precision (QP) division arithmetic which can also process a single, a double and a double-extended precision (SP, DP, DPE) computations. The mantissa division employs a series expansion methodology of division, integrated with a wide integer multiplier further optimized for FPGA implementations facilitating the built-in DSP blocks...
This paper presents an area efficient architecturefor quadruple precision division arithmetic on the FPGAplatform. Many application demands for the higher precisioncomputation (like quadruple precision) than the single anddouble precision. Division is an important arithmetic, butrequires a huge amount of hardware resources with increasingprecision, for a complete hardware implementation. So, thispaper...
Coarse-grained FPGA overlay architectures paired with general purpose processors offer a number of advantages for general purpose hardware acceleration because of software-like programmability, fast compilation, application portability, and improved design productivity. However, the area overheads of these overlays, and in particular architectures with island-style interconnect, negate many of these...
In this paper, we have designed and proposed a new improved Logistic map (ILM) which enhances the performance of the standard Logistic map (SLM) in terms of higher Lyapunov exponent and steady chaotic behavior. In standard map, the control parameter is limited and should be close to 4 to exhibit chaos. Additionally, in some specific region called as islands of stability, the system behaves non-chaotic...
A high performance substitution box (S-Box) FPGA implementation using Galois Field GF (28) is presented in this paper. An optimum number of pipeline registers based on Spartan-3E FPGA is addressed in this paper. The design is fully synthesizable using Verilog and can easily be converted to ASIC implementation. As a result, a fast and area efficient implementation of pipelined S-Box was synthesized...
In this paper, by modifying traditional convolution coder and maximum likelihood decoder based on trellis decoding, a very power efficient coder and decoder is proposed which is compatible for wireless communication system. The hardware implementation of the modified convolution coder and corresponding maximum likelihood decoder is very simple which minimizes complex circuit involvement thus reducing...
Digital Front End Reconfiguration is considered one of the most promising techniques to implement the Software Defined Radio (SDR) and the Cognitive Radio (CR), allowing the same set of hardware to accommodate Multi-Standard Communication Systems (MSCS). The benefit increases when the reconfiguration is not only dynamic but also takes place in real time without the need to switch off the system. This...
An efficient and optimized Distributed Arithmetic (DA)-based method for high-speed reconfigurable design and implementation of Finite Impulse Response (FIR) filters whose filter coefficients change during execution time is proposed in the paper. Normally, the Look up Tables (LUTs) is required to be implemented in RAM for DA-based implementation of reconfigurable FIR Filter. A Dual Port Distributed...
In the past few years, the use of Complementary Set of Sequences (CSS) had a considerable impact on several applications, such as: OFDM or quasi-synchronous CDMA communication systems, multiuser active sensing systems, or the development of non-destructive testing (NDT). Their use is attractive due to the ideal aperiodic correlation properties of the sequences. There are efficient architectures to...
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