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The feasibility of using commercial CMOS processes for implementing scalable cryogenic control electronics for universal quantum computers is investigated. Using a systems engineering approach, we break the system down into sub-systems and model the individual components down to transistor level. First results for area demand and power consumption indicate that even with a standard CMOS process, it...
A CMOS Super class-AB transconductor using Quasi Floating Gates (QFG) techniques to improve the speed and slew rate is presented. The QFG technique is applied to a static DC current source in the classic class-AB OTA, boosting the bias current for large input voltages. The new proposed OTA consumes the same static power as the traditional OTA, however the chip area is increased by 8.5% due to the...
This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic...
In this paper a low power amplifier for bio-signal acquisition is described. The design takes benefit of UTBB-FDSOI 28nm technology and exploits bulk under the buried oxide as a second gate of FET device. This amplifier exhibits low supply current of 25nA, while keeping input noise at 24 µV in bio-signal frequency band. The gain of the amplifier is 71dB.
We propose a new memory-in-pixel (MIP) circuit with only oxide thin-film transistors (Ox-TFTs) for a low-power liquid crystal display with flicker-free feature. The proposed MIP circuit is composed of two new memory circuit units comprising two Ox-TFTs and a capacitor. The proposed memory circuit can modulate the threshold voltage via a simple driving scheme. When the threshold voltage is shifted...
Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity...
Future wireless devices become multi-mode communication systems in order to handle different standards. This paper presents a concurrent dual-band 1.8 and 2.4GHz low noise amplifier (LNA) in response to the growing market demands for more effective LNA's with a low supply voltage and power consumption. The impedance matching of the proposed LNA targeting the Wireless Local Area Network (WLAN) frequencies...
In this paper, a modified low-power bootstrapped sample and hold (S/H) circuit is proposed. The effect of the proposed modified low-power bootstrapped sample and hold (S/H) circuit appears in the medium and high-frequency applications in which it reduces the power consumption without affecting the signal-to-noise and distortion ratio (SNDR). The proposed modified low-power bootstrapped sample and...
A low power switching method for SAR ADC is proposed in this paper. With this switching method the comparator first compares the sampled input voltage with Vref/2 to generate the MSB and determine whether to use Vref/2 or Vref as the comparator reference voltage in the following conversation steps, and the DAC with a split capacitor array uses Vref/2 as the reference voltage to generate the remaining...
This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption...
This paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply...
This paper presents a 10 bit 90 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an asynchronous conversion cycle control. The asynchronous operation allows the sampling rate to be swept over a wide range. The ADC doesn't require any external reference voltages and achieves an excellent performance without the need for calibration. The comparator uses an optimized...
In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. Such a circuit is using a new voltage level shifter topology employing a level-shifting capacitor. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal....
This paper presents a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The proposed switching detect logic can avoid switch power wasted and reduce the impact of capacitor mismatch from the layout parasitic as well as improve the resolution performance of SAR ADC. The ADC consumes 3 uW at 0.5-V supply and 1.28-MS/s sampling rate, achieves high ENOB and FOM...
Clock Distribution Networks (CDNs) in high speed designs can consume 30–50% of the total chip dynamic power. Adiabatic clock circuits can save some of this power, but these depend on a time varying power supply which is difficult to implement in practice. In this paper, we present the first quasi-adiabatic clock circuit with a constant supply voltage at high speeds. Our proposed adiabatic clocks attain...
This paper describes a SAR ADC interface circuit, where the input sensing voltage from a bipolar high voltage domain is linearly translated into the low voltage domain where the SAR ADC operates. The proposed interface circuit employs the principle of charge transfer amplifier to deliver information between two different power domains, in one step, without static power consumption, even if both domains...
This paper presents the implementation of Successive Approximation Architecture (SAR) based Analog to Digital Convertors (ADC). In order to reduce the power consumption and increase the speed, a double-tail latch type comparator is incorporated in the design. Charge redistribution DAC is used for area efficiency. A synchronous type SAR Logic with counter based controlled unit is proposed for faster...
A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented. To reduce the active area and power consumption, front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones. A variable delay loop for enhancing dynamic performances is also included in the ADC. The prototype...
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