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A two-stage power amplifier for UWB systems transmitter was designed and simulated for implementing in standard 0.18-mum CMOS technology. Using cascode scheme and original biasing architecture allows to decrease a number of on-chip inductors and capacitors and simplify amplifier schematic. Amplifier can deliver 30 mW of output power with 48% efficiency in 4-5 GHz bandwidth with 1.8 supply voltage.
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