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In this paper, we compare different existing keeper techniques for reducing power consumption of wide domino logic circuits. We will compare power consumption plus area overhead of each of these methods, with the conventional keeper circuit. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology operating at a frequency of 500 MHz is our test-bench. Simulations show split-domino (SD), with 53%...
Thermometer-to-binary decoders have become the bottleneck in Flash analog-to-digital converters. This paper describes five different 5-bit thermometer-to-binary decoders which are suitable for flash analog-to-digital converter in 1.8 V, 0.18 mum CMOS technology. Comparative study between these thermometer-to-binary decoders is done based on power consumption, count of transistors and delay. The combination...
Reducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the objective of minimizing power consumption of storage using dual-Vdd. Specifically, we propose a complete design framework that starts from dual-Vdd scheduling,...
A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming...
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