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Due to their increasing complexity, the implementation of automation systems faces more challenges. Cognitive architectures have been designed to deal exactly with that. The purpose of a cognitive architecture is to find an action to every possible sensor data to move the system closer to a defined goal. The method is to utilize stored knowledge to reason about the best solution. The challenge for...
Digital-to-Analog converter (DAC) is a fundamental device in data processing systems. It serves as a conversion interface to reconstruct the analog signal from the digital output of the signal processors. In this work, the design and implementation of a 10-bit Segmented Current Steering DAC is carried out at 500 MHz clock frequency and 1.2 V supply voltage. The Segmented architecture provides the...
This work introduces a new general architecture for an analog to digital converter (ADC) cell. Each ADC cell generates one digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage is suitable to be used as an input for another ADC cell in order to produce another digital output bit. This new ADC cell architecture is used as a building block...
In this paper, we propose a novel architecture for next generation cellular networks that enables collaborative forwarding at Layer 2 among adjacent eNBs with the aid of enhanced user equipment (UE) devices, that act voluntarily as packet forwarders. Therefore, legacy UEs are leveraged as active network elements being capable of operating simultaneously over multiple base stations (eNBs). To this...
We describe a tool and methodology for extracting short and effective functional tests from long running commercial programs and manufacturing system tests for testing microprocessors and SOCs. The tool combines fast Instruction Set Architecture (ISA) simulator and Design for Test (DFT) capabilities of the microprocessor to enable tracing of long running workloads. The trace is then converted into...
To overcome physical size limitations in scaling transistors in inherently two-dimensional geometries, efforts are being directed at wafer stacking to implement more quasi three-dimensional (3D) architectures. However, significant and unprecedented gains in terms of packing and speed can be achieved if CMOS components can be integrated in truly 3D cellular porous architectures. In this paper, we present...
Recent penetration of SDR (Software defined radio) technology into mobile systems of new generation as well as increasing throughput demands in radio access network (RAN) are main development engines of new paradigm in radio access network world, better known as Cloud-Radio Access Network (C-RAN). This inovative architecture whose main proponent among telecom companies is China Mobile, should significantly...
As the Integrated Circuit (IC) process improves, the microprocessors become more and more complicated. Most microprocessors allow part of their important parameters to be reconfigured, such as the frequency, cache prefetch mechanism, and so on. Predicting the performance of reconfigurable processor is still an open question since the performance model needs to consider not only program characteristic,...
As one of the main tasks of a project for developing an Advanced Cooperative Info mobility System (ACIS), we have devised and partly implemented a communication middleware for info mobility applications on vehicular ad-hoc networks (VANETs). Our VANET is a wireless network established by the cars themselves, with support from a number of fixed roadside units. Both cars and roadside units are equipped...
The number of Building Integrated Photovoltaic (BIPV) system installations is increasing as different new and specific solar cells and modules are developed. The great advantages of BIPV systems should be enough to achieve their massive implantation, but the difficult working conditions of the urban environment reduce the energy yield and increase the payback period of investment. In order to boost...
Modern NAND Flash-based Solid-State Drives (SSD) presents low latency, high throughput, low power consumption and solid-state reliability improvements comparing to traditional magnetic-disk based Hard Disk Drives (HDD). However, due to NAND Flash memory cell characteristics, update-in-place is impossible. Instead, the Flash software layer allocates new storage space whenever data is written, even...
A general procedure to calculate the stability of the multiport memory cell is proposed. Four novel architectures of the 8-port memory cell are introduced to improve the access time. With the same read access time and silicon area for all the designs, the proposed 6-inverter memory cell has the maximum noise margin.
In order to reconstruct ancient architecture accurately and quickly, a hybrid algorithm combining improved marching cubes with deformable model is adopted in the study based on an optimized spatial grid data structure. After preprocessing such as filter, registration, merging and so on, laser scanning data for reconstructing ancient architecture has become discrete points. So an optimized spatial...
There is a clear trend towards multi-cores to meet the performance requirements of emerging and future applications. A different way to scale performance is, however, to specialize the cores for specific application domains. This option is especially attractive for low-cost embedded systems where less silicon area directly translates to less cost. We propose architectural enhancements to specialize...
Wireless mesh network is emerging as a new generation of wireless network architecture, attracting much research on MAC, routing, application, etc. Widen applied in wide areas, there will produce massive data storage requirements. The paper presents a Hierarchical Storage System on wireless mesh network, with high availability, scalability, self-heal, self-organizing, load balanced. Key technologies...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
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