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Most field programmable gate array (FPGA) devices have a special fast carry propagation logic intended to optimize addition operations. The redundant adders do not easily fit into this specialized carry-logic and, consequently, they require double hardware resources than carry propagate adders, while showing a similar delay for small size operands. Therefore, carry-save adders are not usually implemented...
The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or full-custom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits...
A non-FPGA-based adaptable microarchitecture is presented for fault/defect-tolerance. This paper also introduces an architecture-level fault/defect recovery capability implemented in an adaptable architecture with field-programmable self-repair (FPSR). This FPSR scheme that dynamically cures delay/permanent faults and soft-errors detected at circuit- and architecture-level, respectively, is demonstrated...
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